• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.161-169
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• 2005

This paper presents the new structural Low voltage LVTSCR and TWSCR ESD protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. And the LVTSCR has the triggering voltage of 9V, current of 7mA and can pass below 0.8KV (150mA/um). The triggering voltage of the Triple-well SCR measured to 6V and the current is 40mA. By the substrate and gate bias, the triggering voltage is lowered down to $4{\sim}5.5V$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.573-579
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• 2001

The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high -integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. As devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane by TCAD(Technology Computer Aided Design) to develop optimum device structure. We analyzed and compared the EPI device characteristics such as impact ionization, electric field and I-V curve with those of lightly doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation and the scaling theory is suitable at nano structure device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.311-316
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• 2001

The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. At devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and also newEPI MOSFET for improved structure to weak point of LDD structure by TCAD(Technology Computer Aided Design) to develop optimum device structure. We analyzed and compared the EPI device characteristics such as impart ionization, electric field and I-V curve with those of lightly-doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation and the scaling theory is suitable at nano structure device.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.19 no.6
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• pp.614-619
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• 2009

The STW(servo track writing) system which is the process of writing servo signals on disks before assembling in drives uses the spindle motor-chuck mechanism to realize low cost because the spindle motor-chuck mechanism has merit which can simultaneously write multi-disk by piling up disks in hub. Therefore, when the spindle motor-chuck mechanism of horizontal type operates in high rotation speed it is necessary to reduce the effect of RRO(repeatable run-out) and NRRO(non-repeatable run-out) to achieve the high precision accuracy of nano-meter level during the STW process. In this paper, we analyzed that the slip in assembly surfaces can be caused by the mechanical tolerance and clamping force in hub-chuck mechanism and can affect NRRO performance. We designed springs for centering and clamping considering centrifugal force by the rotation speed and assembly condition. The experimental result showed NRRO performance improves about 30 % than case of weak clamping force. The result shows that the optimal design of the spindle motor-chuck mechanism can effectively reduce the effect of NRRO and RRO in STW process.

• The Science & Technology
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• s.478
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• pp.40-43
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.269-269
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• 2008

• The Science & Technology
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• no.8 s.447
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• pp.18-18
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• 2006

• Proceedings of the Korean Society of Dyers and Finishers Conference
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• 2008.10a
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• pp.113-114
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• 2008

전기방사 방법으로 제조된 나노섬유 부직포를 이용하여 트리코트의 폴리에스터에 워터펀칭한 후, 나노섬유 부직포 형태로 제조하여 패딩방법과 침염방법에 의한 염색성 및 내구성에 관하여 연구 중에 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1022-1025
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• 2003

본 연구에서는 저온 동시 합성법을 이용하여 ITO 나노 분말을 제조하였다. 저온 동시 합성법은 기존의 염화 인듐 및 염화 주석 염이 아닌 인듐 및 주석 유기물 염들을 사용하므로 기존의 $600{\sim}700^{\circ}C$가 아닌 $300^{\circ}C$ 이하에서 공정이 가능하고, 이로써 초미세급의 나노 분말을 얻을 수 있다. 또한 두가지 유기물 염을 동시에 산화시킴으로써 한번에 동시 합성이 가능하다. 이러한 저온 동시 합성법으로 제조한 나노 분말을 분석한 결과 분말의 크기는 평균 5 nm, 비 표면적은 약 $104m^2/g$ 이었다. 또한 EDS 및 XRD 분석 결과 분말의 결정상은 $In_2O_3$ 격자 내에 $3{\sim}8%$의 Sn이 고용된 [222], [400], [440]의 입방정 구조인 고품질의 ITO 나노 분말을 제조할 수 있었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.13-15
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• 2004

The current driven in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure play a significant role and degrade the device performance. These other resistances need to be less than 15％ of the channel resistance. To achieve the requirements, we should investigate the methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.