• Journal of the Korean Vacuum Society
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• v.17 no.1
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• pp.34-39
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• 2008

We have investigated the characteristics of $Al_{0.55}Ga_{0.45}N$/GaN heterostructures with and without low-temperature (LT) AlN interlayer grown by metalorganic chemical vapor deposition. The structural and optical properties were systematically studied by Rutherford backscattering spectroscopy (RBS), X-ray diffraction (XRD), optical microscopy (OMS), scanning electron microscopy (SEM), and photoluminescence (PL). The Al content (x) of 55% and the structural properties of $Al_xGa_{1-x}N$/GaN heterostructures were investigated by using RBS and XRD, respectively. We carried out OMS and SEM experiments and obtained a decrease of the crack network in $Al_{0.55}Ga_{0.45}N$ layer with LT-AlN interlayer. A two-dimensional electron gas (2DEG)-related PL peak located at ${\sim}3.437eV$ was observed at 10 K for $Al_{0.55}Ga_{0.45}N$/GaN with LT-AlN interlayer. The 2DEG-related emission intensity gradually decreased with increasing temperature and disappeared at temperatures around 100 K. In addition, with increasing the excitation power above 3.0 mW, two 2DEG-related PL peaks were observed at ${\sim}3.411$ and ${\sim}3.437eV$. The observed lower-energy and higher-energy side 2DEG peaks were attributed to the transitions from the sub-band level and the Fermi energy level of 2DEG at the AlGaN/LT-AlN/GaN heterointerface, respectively.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.101-108
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• 1993

$TiO_{2}$/Se : Te heterojunction for color sensor has been fabricated by RF reactive sputtering and thermal evaporation methods onto glass substrate. The optimum deposition condition of $TiO_{2}$ films was such that RF power was 120 W, substrate temperature was $100^{\circ}C$, oxygen concentration was 50%, working pressure was 50 mTorr for the $TiO_{2}$ film thickness of $1000{\AA}$. In this case, the optical transmittance of $TiO_{2}$ film at 550 nm-wavelength was 85%, resistivity was $2{\times}10^9{\Omega}{\cdot}cm$, refractive index was 2.3, and optical bandgap was 3.58 eV. The composition ratio of 0 to Ti by AES analysis was 1.7. When $TiO_{2}$ films were annealed at $400^{\circ}C$ for 30 min. in $O_{2}$ ambient, the optical transmittance of $TiO_{2}$ films at the wavelength range of $300{\sim}580$ nm was improved from 0 to 25%. When Se : Te films were annealed at $190^{\circ}C$ for 1 min., photosensitivity under illumination of 1000 lux was 0.75. The optical bandgap of Se : Te films was 1.7 eV. The structures of Se : Te films were the hexagonal with (100) and (110) orientation. The spectral response of a-Se was improved by the addition of Te, especially in the long wavelength region. The $TiO_{2}$/Se : Te heterojunction showed wide spectral response, and more improved one than that of a-Si film in the blue light region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.13-19
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• 2001

We report on the fabrication and characterization of $Al_{0.3}Ga_{0.7}N$ HFETs with different barrier layer thickness which were grown using plasma-assisted molecular beam epitaxy (PAMBE). The barrier thickness of $Al_{0.3}Ga_{0.7}N$/GaN HFETs could be optimized in order to maximize 2 dimensional electron gas induced by piezoelectric effect without the relaxation of $Al_{0.3}Ga_{0.7}N$ layer. $Al_{0.3}Ga_{0.7}N$/GaN (20 nm/2 mm) HFET with 0.6 ${\mu}m$-long and 34 ${\mu}m$-wide gate shows saturated current density ($V_{gs}=1\;V$) of 1.155 A/mm and transconductance of 250 ms/mm, respectively. From high frequency measurement, the fabricated $Al_{0.3}Ga_{0.7}N$/GaN HFETs showed $F_t=13$ GHz and $F_{max}=48$ GHz, respectively. The uniformity of less than 5% could be obtained over the 2 inch wafer. In addition to the optimization of epi-layer structure, the relation between breakdown voltage and high frequency characteristics has been examined.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.6
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• pp.498-507
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• 2017

Electronic equipments comprised of high density components with various packaging types have been recently applied to a satellite. Therefore, to guarantee high reliability of electrical equipment, a design approach, which can reduce the development period and cost through an early diagnosis in potential risks of failure, should be established. In the previous research, the reliability assesment of the electronic equipments have based on Steinberg's fatigue failure theory. However, this theory was not enough for further investigation of life prediction and reliability of the electronic equipments comprised of various sizes and packaging types due to its theoretical limitations and analysis results sensitivity with regard to different modeling technic. In that case, if detailed finite element model is established, aforementioned problems can be readily solved. However, this approach might arise disadvantage of spending much time. In this paper, to establish strategy for high reliability design of electronic equipment, we performed mechanical reliability evaluation of CCB (Camera Controller Box) at qualification level based on the approach using Sherlock unlike design techniques applied to existing business.

• Korean Journal of Materials Research
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• v.20 no.4
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• pp.210-216
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafers. It is observed that the passivation quality of a-Si:H thin-films on c-Si wafers depends highly on the initial H-termination properties of the wafer surface. The effective minority carrier lifetime (MCLT) of highly H-terminated wafer is beneficial for obtaining high quality passivation of a-Si:H/c-Si. The wafers passivated by p(n)-doped a-Si:H layers have low MCLT regardless of the initial H-termination quality. On the other hand, the MCLT of wafers incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with initial cleaning and H-termination schemes. By applying the improved cleaning processes, we can obtain an MCLT of $100{\mu}sec$ after H-termination and above $600{\mu}sec$ after i a-Si:H thin film deposition. By adapting improved cleaning processes and by improving passivation and doped layers, we can fabricate a-Si:H/c-Si heterojunction solar cells with an active area conversion efficiency of 18.42%, which cells have an open circuit voltage of 0.670V, short circuit current of $37.31\;mA/cm^2$ and fill factor of 0.7374. These cells show more than 20% pseudo efficiency measured by Suns-$V_{oc}$ with an elimination of series resistance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.30-37
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• 1989

The PIN type a-SiC:H/a-Si:H heterojunction solar cells were fabricated by using the rf glow discharge decomposition of $SiH_4$ mixed with $CH_4,B_2,H_6\;and\;PH_3.$ The efficiency of the solar cell of the $SnO_2/ITO$ was higher than that of ITO transparent oxide layer by 1.5%. The P layer was prepared with the thickness of $100{\AA}$ and $CH_4/SiH_4$ ration of 5. The I layer has been deposited on the P layer and it is not pure intrinsic but near N type. So $SiH_4$ mixed with $B_2H_6$ of 0.3ppm was used to change this N type nature to intrinsic having the thickness of 5000${\AA}$. And consecutively, the N layer was deposited with t ethickness of $400{\AA}$ using $SiH_4/PH_3$ mixtures. The solar cell demonstrated 0.94V of $V_{oc'}$ 14.6mA/cm of $J_{sc}$ and 58.2% of FF, resulting the efficiency of 8.0%. To minimize loss by the reflection of light, $MgF_2$ layer was coated on the lgass and the efficiency was improved by 0.5%. Therefore, the solar cell indicated overall efficiency of 8.5%.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.93-99
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• 2016

In this paper, we investigated the mechanical and electrical reliability of silver nanowire (AgNW) films. In particular, the durability and reliability of AgNW films were studied when the AgNW film was subjected to the bending deformation under current flow. The electrical durability of AgNW was evaluated by observing changes in heat generation and current density occurring in AgNW through voltage and current tests. The AgNW film showed a constant resistance change up to a bending radius of 2 mm and 200,000 cycles in the bending fatigue tests. The over-coating layer has an effect of improving the durability of the AgNW film. In the case of AgNW with the over-coating layer, heat was uniformly dissipated on the surface of AgNW film, whereas in the case of AgNW film without the over-coating layer, heat was generated locally. In the bending test under the current flow, the current density of the AgNW film was continuously decreased up to 52.4%. During bending, the AgNW was deformed due to mechanical deformation such as tensile, bending and sliding of the AgNW, consequently contact resistance of the AgNW was increased, leading to a electrical breakdown of AgNW by Joule heating. It was found that the application of the over-coating layer can improve the electrical and mechanical reliability of the AgNW film.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.7-13
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• 2007

In the optical module for optical communications, the flip chip bonding is used fer the precise alignment of the optical fiber and optical device. In flip chip bonding, the optical device is aligned and welded while observing the alignment mark of substrate and chip by using flip chip bonder in order to bond the optical device at the exact position. In this research, optical passive alignment method of photodiode(PD) flip chip bonding is suggested for low cost optical subassembly. By using the visible He-Ne laser (633nm wavelength), photodiode is easily aligned with emitting spot on the optical fiber with the help of stereoscopic alignment system. We compensated wavelength dependent deviation about 4m to find out real alignment position of 1550nm input laser by ray tracing. The maximum optical coupling efficiency between the optical fiber and photodiode was about 23.3%.

• Journal of Sensor Science and Technology
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• v.7 no.1
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• pp.67-72
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• 1998

The crystallized CuPc and PbTe films are formed by thermal evaporation and pulsed ArF excimer laser ablation. Structural and electrical properties of thin film is observed by XRD and current-voltage(I-V) curves. From XRD analysis, both PbTe and CuPc thin films show a-axis oriented structure. For the measurement of photovoltaic effect, the transverse current-voltage curve of CuPc/Si, PbTe/Si and PbTe/CuPc/Si junctions have been analyzed in the dark and under illumination. The PbTe/CuPc/Si junction exthibits a strong photovoltaic characteristics with short circuit current($J_{sc}$) of $25.46\;mA/cm^{2}$ and open-circuit voltage($V_{oc}$) of 170 mV. Quantum efficiency and power conversion efficiency are calculated to be 15.4% and $3.46{\times}10^{-2}$, respectively. Based on the results of QE and ${\eta}$, the photocurrent process of PbTe/CuPc/Si junction can be explained as following three effective steps; photocarrier generation in the CuPc layer, carrier separation at PbTe/CuPc interface, and finally a transportation of electrons through the PbTe layer.