• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.5
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• pp.14-20
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• 2006

In recent year, as the robot technology is developed, the researches on the artificial muscle actuator that enables robot to move dexterously like biological organ become active. Actuators are key technologies underpinning robotics. Breakthroughs in actuator technology, particular in terms of power-to-weight ratio, or energy-density, will have significant impacts upon the design and control of robotic system. In this paper, a new approach to design and control of shape memory alloy(SMA) actuator is presented to drive the robot hand. SMA wire is divided into many segments and their thermal states of the SMA are controlled individually in a binary manner. This control manner will reduce the hysteresis that the SMA material has and it becomes the fundamental technology to develop the anthropomorphic robot hand. In this paper, the mechanism In the digital step motor of the shape memory alloy that is driven by the segmented binary control, which is a new control technique, is studied. This SMA digital step actuator applies for the robot hand and the driving mechanism of the robot hand is investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.284-285
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• 2000

광굴절률 현상은 optical signal processing과 홀로그램 기억소자로 널리 응용 될 수 있기 때문에 지금까지 광범위하게 연구되어져 왔다. 광굴절률 현상에서 중요한 변수는 빛이 있는 동안 drift, diffusion 과 photovoltaic current와 같은 전하 운반 메카니즘을 통해서 local charge의 재분포에 따른 공간전하장(Space-charge field, $E_{sc}$ )이다. 지금까지 single beam에 의한 공간전하장을 측정하는 방법으로 birefringenc $e^{1.2}$ 와 interference metho $d^{3}$을 이용하여 굴절률 변화를 측정함으로써 얻을 수 있었다. 그러나 이런 방법들은 공간전하장의 변화를 측정하기위해서 전기광학계수를 측정하여 얻는 간접적인 방법이고 또한 실험방법도 다소 복잡하다. 따라서 본 투고에서는 이미 발표된 광굴절률 현상시 제 2 고조파 세기(SHG)의 변화로부터 공간전하장을 간단하게 측정하는 방법을 이용하여 congruent, MgO가 4mole%, F $e_2$O가 0.1mole% 첨가된 LiNb $O_3$ 단결정의 공간전하장에 대해서 연구를 하였다. 이 방법은 전기광학물질인 LiNb $O_3$에서 SHG 위상정합조건이 dc 전기장에 의존하는 성질을 이용한 것이다. 그리고 온도가 일정할 경우 전기장의 변화에 따라 SHG의 크기가 변함을 이용하였다. (중략)

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.108-114
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• 1995

Recently, along wtih the advance of high-performance system, synchronous DRAM's (SDRAM's) which provide consecutive data output synchronized with an external clock signal, have been reported. However, in the conventional SDRAM's which utilize a multi-stage serial pipelined scheme, the column path is divided into multi-stages depending on CAS latency N. Thus, as the operating speed and CAS latency increase, new stages must be added, thereby causing a large area penalty due to additinal latches and I/O lines. In the proposed register-based parallel pipelined scheme, (N-1) registers are located between the read data bus line pair and the data output buffer and the coming data are sequentially stored. Since the column data path is not divided and the read data is directly transmitted to the registers, the busrt read operation can easily be achieved at higher frequencies without a large area penalty and degradation of internal timing margin. Simulation results for 0.32um-Tech. 4-Bank 64M SDRAM show good operation at 200MHz and an area increment is less than 0.1% when CAS latency N is increased from 3 to 4.. This pipelined scheme is more advantageous as the operating frequency increases.

• Journal of the Korean institute of surface engineering
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• v.27 no.2
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• pp.109-117
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• 1994

Effect of ultrasonic agitation on the contact properties was studied in Ni electroless plating and Pd activation. P-type Si bare wafers were used as substrate and DMAB was used as reducing agent due to its good electrical properties, solderability and compatibility to substrate. In activation, high density Pd nuclei of small size were formed during ultra-sonic agitation compared to that of no stirring. In electroless plating, the plating rate was enhanced by 30∼90% by using ultrasonic agitation. In elecrtoless plating, inhibitor is the most effective additives in ultrasonic agitation. In this experi-ment, thiourea was used as inhibitor. The less the amount of the inhibitor, the more ultrasonic agitation efficiency. It is confirmed by SEM that Ni-B films formed by ultrasonic were coarser, less porous, and denser than those of no stirring. In ultrasonic agitation, boron content of the films was more than those of no stirring. In this case, the more DMAB concentration, the higher the temperature, the less pH, the more boron content. Resistivity of the films formed by ultrasonic agitation was higher than that of no strirring. As the content of boron was increased, the resistivity of the films was increased exponentially.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.329-330
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• 2006

The research and development of an actuator are accelerating in the robotics industry. The electricity polymer and SMA actuator are designed simply and are produced a lot of forces per unit volume. Their motions are similar to human's motion, But the repeatability of the electricity polymer actuator is lower. The reaction velocity of the SMA actuator is slow and the travel is short. In this paper, the dynamic characteristic of the segmented SMA is studied. The SMA wire is divided by using the Thermo-electric module(TEM) to control each of segments independently. The MOSFET circuit is used to supply constant currents fer the Thermo-electric module(TEM). The hysteresis and displacement of the SMA wire according to load are measured.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• Korean Journal of Crystallography
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• v.11 no.2
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• pp.95-101
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• 2000

Ferroelectric SrBi2Ta2O9 (SBT) thin films of Pt/Ti/SiO2 electrode were fabricated using a sintered SBT target with various Bi2O3 content by rf magnetron sputtering. Good hysteresis loop characteristics were observed in the SBT thin films deposited with 50mol% excess Bi target. SBT thin films crystallized from 650℃ however, good hysteresis loop can be obtained in the film annealed above 700℃. pt/TiO2/SiO2 and Pt/SiO2 electrodes were also used to investigate the Pt electrode dependence of SBT thin films. SBT thin films showed random oriented polycrystalline structure and similar morphology regardless of electrodes with quite different surface morphology. A 0.2㎛ thick SBT film annealed at 750℃ exhibited the remanent polarization (2Pr) of μC/㎠ and coercive voltage(Vc) of 1V at an applied voltage of 5V.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.425-432
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• 1995

In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing APTG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In addition, the flip-flops associated with design for testability (DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.