• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.3
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• pp.231-238
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• 2004

This paper presents the high speed noise reduction processing system using the modified discrete fourier transform(MDFT) on the frequency domain. The proposed filter uses the linear prediction coefficients of the adaptive line enhance(ALE) method based on the Sign algorithm The signals with a random noise tracking performance are examined through computer simulations. It is confirmed that the fast adaptive digital filter is realized by the high speed adaptive noise reduction(HANR) algorithm with rapid convergence on the frequency domain(FD).

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.6
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• pp.449-453
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• 2001

In this paper, we propose an algorithm to design the adaptive structure of wavelet neural network with F-projection and geometric growing criterion. Geometric growing criterion consists of estimated error criterion considering local error and angle criterion which attempts to assign a wavelet function that is nearly orthogonal to all other existing wavelet functions. These criteria provide a methodology that a network designer can construct wavelet neural network according to one's intention. We apply the proposed constructing algorithm of the adaptive structure of wavelet neural network to approximation problems of 1-D and 2-D function, and evaluate the effectiveness of the proposed algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.5
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• pp.462-471
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• 2008

Flight recoder is used to analyze the accident factors and prevent the accident. In the analysis of the flight recorder, the most important factor is how to estimate the precise location of the flight. Traditional aviation navigation is based on stable sensors such as DME and VOR. In order to enhance the precision of the location estimation, the integrated navigation algorithm is designed to incorporate DME, Air data sensors and INS(Inertial Navigation System). The results demonstrate that the proposed algorithm can achieve better accuracy, comparing with the traditional navigation schemes, in flight location estimation.

• Communications for Statistical Applications and Methods
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• v.18 no.3
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• pp.391-401
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• 2011

Consider a cluster, so called a 'son cluster', whose mean and variance is composed of the means and variances of both clusters called as a 'father cluster' and a 'mother cluster'. In this paper, a method for identifying each of three clusters is provided by modeling the relationship with father and mother clusters. Under the normal mixture model, the parameters are estimated via EM algorithm. We were able to overcome the problems of estimation using ECM approximation. Numerical examples show that our method can effectively identify the three clusters, so called a 'family of clusters'.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2000.04a
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• pp.724-727
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• 2000

Rapid Prototyping(RP)이란 3차원 솔리드 모델을 단면화한 뒤 하나씩 적층하는 가공방식을 총칭한다. 이때 단면화하는 방법에 따라서 uniform, adaptive slicing으로 나뉘며, 입력 모델에 따라서 direct slicing과 STL을 이용한 방식으로 나뉜다. 적층 방법에 따라서는 연속된 2D 윤곽을 기반으로 적층하는 vertical layer 방식과 인접한 두 개의 2D 윤곽들을 연결하며 만들어진 3D layer를 기반으로 가공하는 sloping layer방식으로 나뉠 수 있다. 현재 상용 RP 시스템들에서는 거의 모든 경우 vertical layer 방식이 채택되어 사용되고 있다. RP와 절삭 공정, 예를 들면 CNC 밀링의 장점을 효율적으로 결합하기 위해서는 임의의 복잡한 형상을 갖는 솔리드 모델을 정밀도에 제한이 없이 제조할 수 있어야 한다. 그러나 절삭 공정은 특별한 전문적 지식들을 필요로 한다 또한 상용 RP에서 사용하는 순차적인 적층 작업으로는 가공할 수 없는 형상들이 많다. 대표적인 것으로 지지대를 필요로 하는 형상들이 있다. 이러한 형상들을 지원하기 위해서는 복잡한 3D 형상을 절삭 가능한 형식으로 분할하는 것과 적층 가능한 순서대로 공정 계획하는 것이 필요하게 된다. 본 연구에서는 SDM에서 제시된 3D 분할 방법이 솔리드 모델을 기반으로 전개되어 STL file과 같은 삼각다면체 형식으로 근사화된 모델에 적용하기 어렵다는데 착안하여 STL file에서 읽어들인 삼각 다면체 모델을 가공 가능한 3D 형상으로 분할하는 알고리즘을 제시하고자 한다.

• Journal of KIISE:Information Networking
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• v.36 no.2
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• pp.98-107
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• 2009

In this paper, we propose a novel centralized energy-efficient clustering algorithm, called "MCCA : Max k-Cut based Clustering Algorithm for Wireless Sensor Networks." The algorithm does not use location information and constructs clusters via a distributive Max k-Cut based cluster-head election method, where only relative and approximate distance information with neighbor nodes is used and nodes, not having enough energy, are excluded for cluster-heads for a specific period. We show that the energy efficiency performance of MCCA is better than that of LEACH, EECS and similar to BCDCP's by simulation studies.

• Journal of the Korea Computer Graphics Society
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• v.18 no.3
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• pp.1-7
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• 2012

In this paper, we propose a method to compute the interface between protein molecules. When a molecules is represented as a set of spheres with van der Waals radii, the distance from a spatial point p to the molecule corresponds to the distance from p to the closet sphere. The molecular interface is composed of equi-distant points from two molecules. Our algorithm decomposes the space into a set of voxels, and then constructs a voxel map by storing the information of spheres intersecting each voxel. By using the voxel map, we compute the distance between a point and the molecule. We also use GPU for the parallel processing, and efficiently approximate the interface of a pair of molecules.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.69-74
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• 2015

In this paper the patterns of information system is reduced so that control rules can guarantee fast response of queries in database. Generally an information system includes many kinds of necessary and unnecessary attribute. In particular, inconsistent information system is less likely to acquire the accuracy of response. Hence we are interested in the simple and understandable rules that can represent useful patterns by means of rough entropy and Bayesian posterior probability. We propose an algorithm which can reduce control rules to a minimum without inadequate patterns such that the implication between condition attributes and decision attributes is measured through the framework of rough entropy. Subsequently the validation of the proposed algorithm is showed through test information system of new employees appointment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8C
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• pp.729-740
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• 2002

This paper studies the issues arising in the virtual topology reconfiguration phase of Multi-wavelength Routed Optical Networks. This reconfiguration process means to change the virtual topology in response to the changing traffic patterns in the higher layer. We formulate the optimal reconfiguration policy as a multi-stage decision-making problem to maximize the expected reward and cost function over an infinite horizon. Then we propose a new heuristic algorithm based on node-exchange to reconfigure the virtual topology to meet the traffic requirement. To counter the continual approximation problem brought by heuristic approach, we take the traffic prediction into consideration. We further propose a new heuristic reconfiguration algorithm called Prediction based Multi-stage Reconfiguration approach to realize the optimal reconfiguration policy based on predicted traffic. Simulation results show that our reconfiguration policy significantly outperforms the conventional one, while the required physical resources are limited.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.35-46
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• 1999

A derotator VLSI which compensates for the frequency and phase errors of a received signal in digital communication systems was developed employing a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. Since a derotator needs only small phase error accumulation, a fast direction sequence generation method which exploits the linearity of the arctangent function in small angles is utilized in order to enhance the operating speed. The chip was designed and implemented using a $0.6\mu\textrm{m}$ triple metal CMOS process by the full custom layout method. The whole chip size is $6.8\textrm{mm}^2$ and the maximum operating frequency is 25 MHz.