• Title/Summary/Keyword: 공정가산율

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사학연금의 연기연금제도 도입 검토 : 연금수급 연기 시 가산율의 설정 문제를 중심으로

  • Kim, Won-Seop
    • Journal of Teachers' Pension
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    • v.3
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    • pp.255-278
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    • 2018
  • 본 연구는 사학연금에서 연기연금재도의 도입 필요성을 검토하고 특히 도입 시 적용할 가산율 설정 등 구체적인 도입방안을 제시하고자 하였다. 사학연금에서 연기연금제도는 수급자의 근로유인과 활동적 노년의 진작을 위해서 필요하다. 이는 또한 국민연금과 직역연금이 동조화되고 있는 현 추세와도 일치한다. 이 연구는 또한 국민연금의 연기연금제도를 참고하여 보험수리적 중립성에 입각한 공정가산율을 산출하였다. 이 방식에 따르면 사학연금 연기연금제도의 핵심제도인 공정가산율은 6.2%로 나타났다.

Design of a $54{\times}54$-bit Multiplier Based on a Improved Conditional Sum Adder (개선된 조건 합 가산기를 이용한 $54{\times}54$-bit 곱셈기의 설계)

  • Lee, Young-Chul;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.67-74
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    • 2000
  • In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

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High-Speed Low-Complexity Two-Bit Level Pipelined Viterbi Decoder for UWB Systems (UWB시스템을 위한 고속 저복잡도 2-비트 레벨 파이프라인 비터비 복호기 설계)

  • Goo, Yong-Je;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.125-136
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    • 2009
  • This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

Studies on the Calculating Method of Conditioned Weight by dry Weight after Boiling-off in Raw Silk (생사정량산정에 있어서 연감후 무수량의 도입에 관한 연구)

  • 김수현;이상근;김영진
    • Journal of Sericultural and Entomological Science
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    • v.13 no.1
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    • pp.73-78
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    • 1971
  • The purpose of this study is to find out the method of conditioned weight test by which the dealing weight of raw silk can be calculated from true fiber in order to do the fair trading. The results of this study were as follows. 1. It is more reasonable than the current test that conditioned weight as a dealing weigh can be calculated by boil-off and moisture regain which is a percentage of boil-on and moisture regain to net weight. Because the boil-off and moisture regain can show directly the amount of true fiber and reproductibility in raw silk. In this study the boil-off and moisture regain is to take dry weight after boiling-off from net weight. 2. To calculate the conditioned weight from boil-of and moisture regain it would be proper that the standard additional ratio is 44 per cent of dry weight after boiling-off. 3. Boil-of percent of the sizing sample skein used in the size test did not show a statistical significance comparing with the boil-off percent of sample skeins (24 skeins) which may represent that of a lot. To observe this result boil-off percent of the sizing sample skein may represent that of a lot. 4. In Korea if conditioned weight test substitute for test of boil-off and moisture regain, we make a profit of two billion won in a year at the current market-price.

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