• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.328-332
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• 2006

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.75-80
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• 2009

RSA cryptoprocessors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, a fast 32bit modular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• Proceedings of the Korea Contents Association Conference
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• 2005.11a
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• pp.389-392
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• 2005

Boolean matrices are applied to a variety of areas and used successfully in many applications. There are many researches on the application and multiplication of boolean matrices. Most researches deal with the multiplication of boolean matrices, but all of them focus on the multiplication of just two boolean matrices and very few researches deal with the multiplication of many pairs of two boolean matrices. The paper discusses it is not suitable to use for the multiplication of many pairs of two boolean matrices the algorithm for the multiplication of two boolean matrices that is considered optimal up to now, and suggests a method that can improve the multiplication of a $n{\times}m$ boolean matrix and all $m{\times}k$ boolean matrices.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.4B
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• pp.418-422
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• 2001

4-점 리버스 자켓 변환 (4-Point Reverse Jacket transform)의 장점 중의 하나는 4-점 fast Fourier transform(FFT)시 야기되는 실수 또는 복소수 곱셈을 행렬분해(matrix decomposition)를 이용, 곱셈인자를 모두 대각행렬에만 집중시킨, 매우 간결하고 효율적인 알고리즘이라는 점이다. 본 논문에서는 이를 N 점 FFT에 적용하는 알고리즘을 제안한다. 이 방법은 기존의 다른 변환형태보다 확장하거나 구조를 파악하기에 매우 용이하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2365-2371
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• 1998

Discrete cosine transform (DCT) has wide applications in speech and image coding. In this paper, we propose a novel fast dCT scheme with the property of reduced multiplication stages and the smaller number of additions and multiplications. This exploits the symmetry property of the DCT kernel to decompose the N-point dCT to N/2 point, and can be generally applied recursively to $2^{m}$-point. The proposed algorithm has a structure that most of multiplications tend to be performed at final stage, and this reduces propagation of truncation error which could occur in the fixed-point computation. Also the minimization of the multiplication stages further decreases the error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of Elementary Mathematics Education in Korea
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• v.22 no.4
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• pp.475-496
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• 2018

Although the multiplication of decimal fractions is expected to be easy for students to understand because of the similarity to natural numbers multiplication in computing methods, students show many errors in the multiplication of decimal fractions. This is a result of the instruction focused more on skill mastery than conceptual understanding. This study is a basic study for effectively developing a unit of multiplication of decimal fractions. For this purpose, we analyzed the curriculums' performance standards, significance in teaching-learning and evaluation, contents and methods for teaching multiplication of decimal fractions from the 7th curriculum to the revised curriculum of 2015 and the textbooks' activities and lessons. Further, we analyzed preceding studies and introductory books to suggest effective directions for developing teaching unit. As a result of the analysis, three implications were obtained: First, a meaningful instruction for estimation is needed. Second, it is necessary to present a visual model suitable for understanding the meaning of decimal multiplication. Third, the process of formalizing an algorithms for multiplying decimal fractions needs to be diversified.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.190-194
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• 2002

Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.