• Title/Summary/Keyword: 곱셈

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Performance Analysis of Matrix Multiplications for Big Data (빅 데이터를 위한 행렬 곱셈의 성능 분석)

  • Kwon, Il-Taek;Jo, Yong-Yong;Kim, Sang-Wook
    • Annual Conference of KIPS
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    • 2014.11a
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    • pp.747-749
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    • 2014
  • 행렬 곱셈은 다양한 사회연결망을 포함한 빅 데이터 분석에 핵심이 되는 연산 중 하나이다. 본 연구에서는 행렬 곱셈 방법 중 내적과 행-행 곱셈에 대한 성능 분석과 실제 사회연결망 데이터 셋을 이용한 행렬 곱셈 시간을 분석한다. 본 연구의 실험환경에서 행렬 곱셈 방법 중 행-행 곱셈이 내적보다 약 125 배 빠르다는 것을 확인했고, 실제 사회연결망 데이터 셋을 행렬 곱셈했을 때의 시간은 읽기, 쓰기 등 저장장치 접근 시간이 행렬 곱셈 전체 수행 시간의 약 90% 이상 차지한다는 것을 확인했다. 따라서 사회연결망 데이터 분석을 위한 행렬 곱셈에서 저장 장치 접근 시간을 줄이는 것이 전체 계산 수행 시간을 줄이는 것의 핵심임을 이야기한다.

Design of Low Error Fixed-Width Group CSD Multiplier (저오차 고정길이 그룹 CSD 곱셈기 설계)

  • Kim, Yong-Eun;Cho, Kyung-Ju;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.9
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    • pp.33-38
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    • 2009
  • The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

An Efficient Bit-Parallel Normal Basis Multiplier for GF(2$^m$) Fields Defined by All-One Polynomials (All-One 다항식에 의한 정의된 유한체 GF(2$^m$) 상의 효율적인 Bit-Parallel 정규기저 곱셈기)

  • 장용희;권용진
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04a
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    • pp.272-274
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    • 2003
  • 유한체 GF(2$^{m}$ ) 상의 산술 연산 중 곱셈 연산의 효율적인 구현은 암호이론 분야의 어플리케이션에서 매우 중요하다. 본 논문에서는 All-One 다항식에 의해 정의된 GF(2$^{m}$ ) 상의 효율적인 Bit-Parallel 정규기저 곱셈기를 제안한다. 게이트 및 시간 면에서 본 논문의 곱셈기의 complexity는 이전에 제안된 같은 종류의 곱셈기 보다 낮거나 동일하다. 그리고 본 논문의 곱셈기는 이전 곱셈기 보다 더 모듈적이어서 VLSI 구현에 적합하다.

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A Fast Method for Computing Multiplicative Inverses in $GF(2^{m})$ Using Normal Basis ($GF(2^{m})$에서 정규기저를 이용한 고속 곱셈 역원 연산 방법)

  • 장용희;권용진
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 2002.11a
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    • pp.84-87
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    • 2002
  • 최근 정보보호의 중요성이 커짐에 따라 암호이론에 대한 관심이 증가되고 있다. 이 중 Galois 체 GF(2$^{m}$ )은 대부분의 암호시스템에서 사용되며, 특히 공개키 기반 암호시스템에서 주로 사용된다. 이들 암호시스템에서는 GF(2$^{m}$ )에서 정의된 연산, 즉 덧셈, 뺄셈, 곱셈 및 곱셈 역원 연산을 기반으로 구축되므로, 이들 연산을 고속으로 계산하는 것이 중요하다. 이들 연산 중에서 곱셈 역원이 가장 time-consuming하다. Fermat의 정리를 기반으로 하고, GF(2$^{m}$ )에서 정규기저를 사용해서 곱셈 역원을 고속으로 계산하기 위해서는 곱셈 횟수를 감소시키는 것이 가장 중요하며, 이와 관련된 방법들이 많이 제안되어 왔다. 이 중 Itoh와 Tsujii가 제안한 방법[2]은 곱셈 횟수를 O(log m)까지 감소시켰다. 본 논문에서는 Itoh와 Tsujii가 제안한 방법을 이용해서, m=2$^n$인 경우에 곱셈 역원을 고속으로 계산하는 방법을 제안한다. 본 논문의 방법은 필요한 곱셈 횟수가 Itoh와 Tsujii가 제안한 방법 보다 적으며, m-1의 분해가 기존의 방법보다 간단하다.

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Development of Hardware Modules for Montgomery Modular Multipliers based on 32-bit multipliers (32 비트 곱셈기에 기반한 몽고메리 모듈러 곱셈기 하드웨어 모듈 개발)

  • 양인제;김동규
    • Proceedings of the Korea Multimedia Society Conference
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    • 2003.11a
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    • pp.162-165
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    • 2003
  • RSA 등의 공개키 암호화 시스템에서는 매우 큰 정수에 대해서 모듈러 멱승을 수행한다. 그러므로 모듈러 멱승을 효율적으로 구현하기 위하여 많은 연구가 진행되어 왔다. 모듈러 멱승을 소프트웨어적으로 구현할 경우 시간적인 제약을 극복하지 못하므로, 이를 하드웨어로 구현하려는 연구도 많이 이루어지고 있는 추세이다. 몽고메리 곱셈 알고리즘은 비용이 많이 드는 모듈러 연산을 효율적으로 처리하고 있으므로 하드웨어적 구현에 현재 널리 쓰이고 있다. 몽고메리 곱셈 알고리즘은 내부적으로 당연히 곱셈연산을 주로 사용하기 때문에, 어떤 곱셈기를 사용하느냐가 성능에 영향을 미치게 한다. 본 논문에서는 몽고메리 곱셈기를 다양한 32비트 곱셈기를 적용해 보고, 성능 및 면적을 측정하였다. 이러한 측정 결과를 토대로 특정 응용에 알맞은 32비트 곱셈기를 적절히 선택하여 설계할 수 있을 것으로 기대한다.

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An Investigation on the Historical Developments of the Algorithms for Multiplication of Natural Numbers (자연수 곱셈 계산법의 역사적 발달 과정에 대한 고찰)

  • Joung, Youn-Joon
    • School Mathematics
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    • v.13 no.2
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    • pp.267-286
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    • 2011
  • In this paper I investigated the historical developments of the algorithms for multiplication of natural numbers. Through this analysis I tried to describe more concretely what is to understand the common algorithm for multiplication of natural numbers. I found that decomposing dividends and divisors into small numbers and multiplying these numbers is the main strategy for carrying out multiplication of large numbers, and two decomposing and multiplying processes are very important in the algorithms for multiplication. Finally I proposed some implications based on these analysis.

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A Study of the Development of Children's Multiplication Strategies and the Computational Resources (초등학교 저학년 학생의 곱셈 전략 발달에 관한 연구)

  • Kim, Nam-Gyun;Kim, Ji-Eun
    • School Mathematics
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    • v.11 no.4
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    • pp.745-771
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    • 2009
  • To acquire the hints of the development of children's multiplication strategies, this study tried to find the differences between the students who learned multiplication and the students who didn't. And we also tried to explore their acquired computational resources. As a result, we confirm that there is a certain direction on the development of children's multiplication strategies according to their grades and the level of acquirement of mathematical knowledge. Moreover, we comprehend that commutative law is an important part of the strategies on two-digit multiplication and that acquisition of the computational resources must precede the learning of multiplication strategies. In the end part, this article proposes a new taxonomy of strategies for multiplication. To support our proposal, we integrated the prior researches with our findings.

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Fast GF(2m) Multiplier Architecture Based on Common Factor Post-Processing Method (공통인수 후처리 방식에 기반한 고속 유한체 곱셈기)

  • 문상국
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1188-1193
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    • 2004
  • So far, there have been grossly 3 types of studies on GF(2m) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. Serial multiplication method was first suggested by Mastrovito (1), to be known as the basic CF(2m) multiplication architecture, and this method was adopted in the array multiplier (2), consuming m times as much resource in parallel to extract m times of speed. In 1999, Paar studied further to get the benefit of both architecture, presenting the hybrid multiplication architecture (3). However, the hybrid architecture has defect that only complex ordo. of finite field should be used. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software. The implemented GF(2m) multiplier shows t times as fast as the traditional one, if we modularized the numerical expression by t number of parts.

3X Serial GF($2^m$) Multiplier Architecture on Polynomial Basis Finite Field (Polynomial basis 방식의 3배속 직렬 유한체 곱셈기)

  • Moon, Sang-Ook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.2
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    • pp.328-332
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    • 2006
  • Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

Probability distribution-based approximation matrix multiplication simplification algorithm (확률분포 생성을 통한 근사 행렬 곱셈 간소화 방법)

  • Kwon, Oh-Young;Seo, Kyoung-Taek
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.11
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    • pp.1623-1629
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    • 2022
  • Matrix multiplication is a fundamental operation widely used in science and engineering. There is an approximate matrix multiplication method as a way to reduce the amount of computation of matrix multiplication. Approximate matrix multiplication determines an appropriate probability distribution for selecting columns and rows of matrices, and performs approximate matrix multiplication by selecting columns and rows of matrices according to this distribution. Probability distributions are generated by considering both matrices A and B participating in matrix multiplication. In this paper, we propose a method to generate a probability distribution that selects columns and rows of matrices to be used for approximate matrix multiplication, targeting only matrix A. Approximate matrix multiplication was performed on 1000×1000 ~ 5000×5000 matrices using existing and proposed methods. The approximate matrix multiplication applying the proposed method compared to the conventional method has been shown to be closer to the original matrix multiplication result, averaging 0.02% to 2.34%.