• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.502-510
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• 2009

Multiprecision squaring is one of the most significant algorithms in the core public key cryptography operation. The aim of this work is to present a new improved squaring algorithm compared with the MIRACL's multi precision squaring algorithm in which the previous work [1] on multiprecision multiplication is implemented. First, previous works on multiprecision multiplication and standard squaring are analyzed. Then, our new Lazy Doubling squaring algorithm is introduced. In MIRACLE library [3], Scott's Carry-Catcher Hybrid multiplication technique [1] is applied to implementation of multiprecision multiplication and squaring. Experimental results of the Carry-Catcher hybrid squaring algorithm and the proposed Lazy Doubling squaring algorithm both of which are tested on Atmega128 CPU show that proposed idea has achieved significant performance improvements. The proposed Lazy Doubling Squaring algorithm reduces addition instructions by the fact $a_0\;{\ast}\;2\;+\;a_1\;{\ast}\;2\;+\;...\;+\;a_{n-1}\;{\ast}\;2\;+\;a_n\;{\ast}\;2\;=\;(a_0\;+\;a_1\;+\;...\;+\;a_{n-1}\;+\;a_n)\;{\ast}\;2$ while the standard squaring algorithm reduces multiplication instructions by the fact $S_{ij}\;=\;x_i\;{\ast}\;x_j\;=\;S_{ij}$. Experimental results show that the proposed squaring method is 25% faster than that in MIRACL.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.727-738
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• 2015

Until recently, power analysis is one of the most popular research issues among various side channel analyses. Since Differential Power Analysis had been first proposed by Kocher et al., various practical power analyses correspond with software/hardware cryptographic devices have been proposed. In this paper, we analyze vulnerability of countermeasure against power analysis exploiting single power trace of public cryptographic algorithm. In ICICS 2010, Clavier et al. proposed Horizontal Correlation Analysis which can recover secret information from a single exponentiation trace and corresponding countermeasures. "Blind operands in LIM", one of their countermeasures, exploits additive blinding in order to prevent leakage of intermediate value related to secret information. However, this countermeasure has vulnerability of having power leakage that is dependant with the message known by an adversary. In this paper, we analyzed vulnerabilities by three attack scenarios and proved them by practical correlation power analysis experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8A
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• pp.1348-1357
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• 2001

본 논문에서는 DAB 시스템에서 사용하는 FEC(Forward Error Correction) 블록을 하드웨어 크기를 고려하여 효율적인 구조를 갖도록 설계하였다. DAB 시스템의 FEC 블록은 크게 스크램블러(에너지분산), 리드-솔로몬 코더, 길쌈 인터리버로 구성된다. RS 디코더 블록 중 키 방정식을 계산해 내는 블록과 길쌈 인터리버가 차지하는 하드웨어 비중은 굉장히 크다. 본 논문에서는 스크램블러 부분에서 데이터의 시작을 알려주는 신호의 효율적인 검출기법을 제안하고, 리드-솔로몬 디코더 블록의 수정 유클리드 알고리즘을 효율적인 하드웨어로 구현하기 위한 새로운 구조와 길쌈 인터리버에서 최적의 메모리 구조를 효과적인 구조를 제안한다. 제안한 구조에서는 단지 8개의 GF 곱셈기와 4개의 덧셈기만을 가지고 RS 디코더의 수정 유클리드 알고리즘을 구현하였으며, 2 RAM(128)과 4 RAM(256)을 가지고 컨벌루셔널 인터리버를 구현하였다. 제안한 구조로 설계했을 경우 디코더 블록이 Altera-FPGA 칩(FLEX10K)에 모두 들어갈 수 있었다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.339-342
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• 2005

동적 부분 재구성은 FPGA 칩에 구현된 디자인에서 변경이 필요한 부분만 재구성하여 줌으로써 실시간적 재구성을 가능하게하는 방법이다. 동적 부분 재구성에 대한 많은 연구를 통하여 게이트 수준의 부분 재구성이 가능하지만, 설계 복잡도가 큰 시스템을 설계시에 게이트 수준의 부분 재구성 방법은 부적적하다. 본 논문에서는 Xilinx에서 제고하는 버스 매크로를 사용하여 모듈 기반의 부분 재구성 기법에 대하여 기술하며, 곱셈기, 레지스터, 그리고 ripple carry adder로 구성된 회로에서 ripple carry adder를 carry lookahead adder로 재구성한다.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.436-438
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• 2005

본 논문에서는 전력선 위상 측정을 위해 A/D 변환기 및 위상계측 연산장치를 집적한 하이브리드 센서칩의 구현 기법을 제시하였다. 개발한 위상계측 연산장치는 recursive sliding-DFT에 기반하였으며 곱셈기의 시분할 공유 구조를 사용하여 칩의 구현 면적을 최소화 하였다. 60Hz의 전력선 신호를 중심주파수로 하는 AD 변환장치는 sigma-delta ADC를 기반으로 하여 8-bit 정밀도를 제공하며 아날로그부의 구현을 최소화하도륵 설계하였다. 설계한 하이브리드 센서칩은 컴퓨터 시뮬레이션 및 FPGA 구현을 통해 동작을 검증하였으며, 검증 완료후 $0.35{\mu}m$ CMOS 공정기술로 구현하였다. 전력선 위상을 측정하기 위해 구현된 4채널 하이브리드 센서 칩의 설계면적은 $5{\times}5m^2$ 의 약 20%정도를 차지하였다.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.497-500
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• 2003

In this paper, a new filter structure to improve frequency response characteristics in CIC(Cascaded Integrator-Comb) decimation filters is proposed. Conventional filters improve passband characteristics, but they make worse slinging band characteristics. In this paper, we propose a new filter which is called IFOP(Interpolated Fourth-Order Polynomials). By using this proposed filter, passband droop and aliasing band attenuation are simultaneously improved. Since proposed filter needs only one multiplication computation is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, implementation cost of the proposed filter is compared with those of conventional filters.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.27-35
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• 1997

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1789-1794
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• 2003

Transient and asymmetric density distributions have been investigated by digital speckle tomography. Multiple CCD images captured movements of speckles in three angles of view simultaneously because the flows were asymmetric and transient. The speckle movements between no flow and downward butane flow from a circular half opening have been calculated by a cross-correlation tracking method so that those distances can be tranferred to deflection angles of laser rays for density gradients. The three-dimensional density fields have been reconstructed from the fringe shift by a real-time multiplicative algebraic reconstruction technique (MART).

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.151-162
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• 1995

보다 짧은 길이의 덧셈/뺄셈 사슬($addition_{traction-chain}$)을 찾는 문제는 정수론을 기반으로 하는 많은 암호시스템들에 있어서 중요한 문제이다. 특히, RSA에서의 모듈라멱승(modular exponentiation)이나 타원 곡선(elliptic curve)에서의 곱셈 연산시간은 덧셈사슬(addition-chain) 또는 덧셈/뺄셈 사슬의 길이와 정비례한다 본 논문에서는 덧셈/뻘셈 사슬을 구하는 새로운 알고리즘을 제안하고, 그 성능을 분석하여 기존의 방법들과 비교한다. 본 논문에서 제안하는 알고리즘은 작은윈도우(small-window) 기법을 기반으로 하고, 뺄셈을사용해서 윈도우의 개수를 최적화함으로써 덧셈/뺄셈 사슬의 길이를 짧게 한다. 본 논문에서 제안하는 알고리즘은 512비트의 정수에 대해 평균길이 595.6의 덧셈/뺄셈 사슬을 찾는다.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.1985-1996
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• 1998

A parallelising algorithm for partitioning and mapping methods of matrix/vector multiplication into linear processor array/VLW simulator is presented in this paper. First we discuss the mapping methods for input matrix or vector into the arbitrarily size of processor arrays. Then, we show partitioning the algorithmss of the large size of computational problem into the size of the processor array. We execute the algorithm on VLIW simuhator and show to effectiviness of algorithm. The result which we achived better parallelising performance on our VLIW simulator dsign than on linear processor array.