• Title/Summary/Keyword: 고속 라우터

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An Improvement on Control Data Transmission Method for Performance Elevation of Router (라우터의 성능향상을 위한 제어 데이터 전송방법 개선)

  • Youn, Chun-Kyun
    • Proceedings of the Korea Information Processing Society Conference
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    • 2005.11a
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    • pp.1283-1286
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    • 2005
  • 최근의 대용량 다중 분산 라우터 시스템은 다수의 라인 인터페이스 모듈들과 라우팅 처리 모듈, 스위칭 패브릭 모듈로 구성되어 있고, 고속의 패킷 스위칭 및 라우팅을 구현하기 위하여 일반적으로 입력 패킷을 외부로 전송하기 위한 기능과 제어 및 관리 기능을 담당하는 기능으로 분리하여 실행되고 있다. 이러한 라우터에서는 내부 모듈들의 프로세서들 사이에 정보 송수신을 위해 프로세서 간 통신(IPC : Interprocess Communication)이 이용되고 있다. 라우터의 기능 중 제어 및 관리 기능은 신속한 처리를 위하여 UDP/IP 방식의 IPC 가 사용되고 있는데, 이 UDP/IP 방식을 개선 방안을 제안하고 prototype 시스템을 구현하여 시험한 결과 라우터의 데이터 round trip 시간과 throughput 이 각각 15.1%, 4.3%의 개선되어 라우터의 성능이 향상되었다.

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Optical Transceiver Technology and Its Trend (광트랜시버 기술 및 동향)

  • Lee, J.K.;Kim, K.J.
    • Electronics and Telecommunications Trends
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    • v.24 no.1
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    • pp.12-23
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    • 2009
  • 광트랜시버는 광전송 시스템, 대용량 라우터 및 스위치 등의 광통신 장치에서 전기 신호를 광신호로 바꿔 광섬유를 매체로 송신하며 송신된 광신호를 수신하여 다시 전기 신호로 바꿔주는 광송신과 광수신 기능을 담당하는 모듈을 말한다. 광 송수신 모듈은 초창기 155M, 622M, 2.5 Gb/s SDH/SONET 시스템에 사용되었을 때에는 광송신기와 광수신기가 분리되어 있는 구조였으나, 2000년 이후에 들어서서 광송신기와 수신기가 하나의 패키지 안에 구현된 지금의 광트랜시버 모듈이 등장하였다. 또한, 광트랜시버 모듈 업체를 중심으로 시스템 업체, 부품업체들이 모여 산업체 표준(MSA)을 정하면서 개발 비용과 시간 단축의 효과를 거두는 동시에, 기술면에서도 비약적인 발전을 거듭하고 있다. 이러한 광트랜시버의 발전 방향은 고속화, 소형화, 고성능화, 저가격화로 요약할 수 있다. 본 고에서는 10 Gb/s, 40 Gb/s, 100 Gb/s 광트랜시버를 중심으로 기술동향을 설명하고, 광트랜시버를 개발하는 데 필요한 요소기술에 관하여 살펴본다.

A Study on Reducing Buffer for VC-Merge Capable ATM Switch (VC-Merge Capable ATM Switch의 버퍼용량 축소에 관한 연구)

  • 유정욱;조양현;오영환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.6A
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    • pp.1060-1066
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    • 2001
  • 레이어2 스위칭과 레이어3 라우팅의 통합 모델로써 MPLS(Multi-Protocol Label Switching) 환경에서 ATM LSR(Label-Switching Routers)은 백본망에서의 고속 전송이 가능하여 현재의 라우터 구조로써 제안되어지고 있다. MPLS가 코어 라이터로써 적용이 될 경우 확장성을 위해 label merging이라는 기술이 필요하다. VC(Virtual Circuit) merging은 ATM LSR에서 많은 IP 라우터를 하나의 라벨로 매핑을 시키며 수천 개의 목적지에 전송할 수 있는 확장성 있는 매핑 기술이다. VC merging은 같은 목적지인 다른 패킷들 간의 셀들의 섞임을 방지하기 위해 재 조합 버퍼가 요구된다. 재 조합 버퍼 사용시 일시적인 체증 현상이 발생하며 Non-VC merging과 비교시 많은 셀 손실과 많은 버퍼를 요구하게 된다. 본 논문에서는 RED(Random Early Detection) 알고리즘을 적용하여 VC merging이 필요한 버퍼의 요구량과 셀 손실을 줄였다.

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A UDT Throughput Improvement Method based on Network Delay Prediction (네트워크 지연 예측을 통한 UDT 성능향상 기법)

  • Park, Jong-Seon;Koh, Kwang-Sin;Cho, Gi-Hwan
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.721-724
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    • 2011
  • UDT(UDP-based Data Transfer protocol)는 연구망과 같은 대용량 고속 네트워크에서 신속하고 안정적인 데이터 전송에 효율적인 전송 프로토콜이다. 하지만 네트워크가 혼잡한 상황이거나 데이터 패킷 손실이 발생할 경우 매우 공격적인 전송 메커니즘으로 인해 오히려 성능이 감소하는 경우가 발생한다. 본 논문에서는 네트워크 지연 예측을 통해 혼잡을 제어하는 TCP-Vegas 기법을 UDT에 적용하여 네트워크 상황에 보다 적응적인 UDT 혼잡제어 기법을 제안한다. 즉, 네트워크 라우터 큐에 빌드된 Diff 값을 미리 예측하고 Diff 값에 따라 UDT rate control을 조절하여 기존 방법보다 향상된 성능을 얻는다. 네트워크 시뮬레이터인 NS2를 통해 실험한 결과 패킷 손실이 없는 상황에서 최대 11%, 손실률 0.01%인 상황에서는 최대 31%의 성능 향상을 확인하였다.

An Efficient Update Algorithm for Packet Classification With TCAM (TCAM을 이용한 패킷 분류를 위한 효율적인 갱신 알고리즘)

  • Jeong Haejin;Song Ilseop;Lee Yookyoung;Kwon Taeckgeun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.2A
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    • pp.79-85
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    • 2006
  • Generally, it is essential that high-speed routers, switches, and network security appliances should have an efficient packet classification scheme in order to achieve the high-speed packet forwarding capability. For the multi-gigabit packet-processing network equipment the high-speed content search hardware such as TCAM and search engine is recently used to support the content-based packet inspection. During the packet classification process, hundreds and thousands of rules are applied to provide the network security policies regarding traffic screening, traffic monitoring, and traffic shaping. In addition, these rules could be dynamically changed during operations of systems if anomaly traffic patterns would vary. Particularly, in the high-speed network, an efficient algorithm that updates and reorganizes the packet classification rules is critical so as not to degrade the performance of the network device. In this paper, we have proposed an efficient update algorithm using a partial-ordering that can relocate the dynamically changing rules at the TCAM. Experimental results should that our algorithm does not need to relocate existing rules feature until 70$\%$ of TCAM utilization.

Implementation of High Performance Overlay Multicast Packet Forwarding Engine On NetFPGA (NetFPGA를 이용한 고성능 오버레이 멀티캐스트 패킷 전송 엔진 구현)

  • Jeon, Hyuk-Jin;Lee, Hyun-Seok;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.6
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    • pp.9-17
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    • 2012
  • High-quality multimedia on the Internet has attracted attention because of its wide application area. IP multicast has been proposed as a solution to use efficient network resources in these services. However, IP multicast has not been commonly used due to a number of practical issues such as security and management. As an alternative, an overlay multicast routing which is performed in upper protocol layers on legacy networks without changing hardware has been presented. Yet, the maximum data transmission capacity of the overlay multicast is not sufficient for real time transmission of multimedia data. In this paper, we have implemented an overlay multicast engine on NetFPGA which allows us to perform packet replication and tunneling which need high-speed. In addition, we have implemented extra portions which need low-speed in software. From now on, we will progress research which increase the number of terminal spots which can be replicated by improvement and amplify throughputs by optimization.

Enhanced Bitmap Lookup Algorithm for High-Speed Routers (고속 라우터를 위한 향상된 비트맵 룩업 알고리즘)

  • Lee, Kang-woo;Ahn, Jong-suk
    • The KIPS Transactions:PartA
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    • v.11A no.2
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    • pp.129-142
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    • 2004
  • As the Internet gets faster, the demand for high-speed routers that are capable of forwarding more than giga bits of data per second keeps increasing. In the previous research, Bitmap Trie algorithm was developed to rapidly execute LPM(longest prefix matching) process which is Well known as the Severe performance bottleneck. In this paper, we introduce a novel algorithm that drastically enhanced the performance of Bitmap. Trie algorithm by applying three techniques. First, a new table called the Count Table was devised. Owing to this table, we successfully eliminated shift operations that was the main cause of performance degradation in Bitmap Trie algorithm. Second, memory utilization was improved by removing redundant forwarding information from the Transfer Table. Lastly. the range of prefix lookup was diversified to optimize data accesses. On the other hand, the processing delays were classified into three categories according to their causes. They were, then, measured through the execution-driven simulation that provides the higher quality of the results than any other simulation techniques. We tried to assure the reliability of the experimental results by comparing with those that collected from the real system. Finally the Enhanced Bitmap Trie algorithm reduced 82% of time spent in previous algorithm.

Analyses of Hardware Architecture for High-speed VPN System (VPN 시스템 고속화를 위한 하드웨어 구조 분석)

  • 김정태;허창우;한종욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.7
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    • pp.1471-1477
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    • 2003
  • In order to realize the Gbps VPN system, however, newer and more advanced technologies are required to enable wire-rate processing across a wide range of functions and layers. While it is generally accepted that a software soluTion on general-purpose processors cannot scale to process these functionsa wire rate, the KEY POINT is that a software solution on general-purpose processors is the most practical way by which these security allocationscan be developed. Many of these security functions require application layer processing on the content of the packets, and the very nature of application layer software development is characterized by relatively large code size with a high need for portability an flexibility. We have analysed the consideration and specification for realizing Gbps VPN system. from this work. we can obtain a technology of originality.

A Bit-Map Trie for the High-Speed Longest Prefix Search of IP Addresses (고속의 최장 IP 주소 프리픽스 검색을 위한 비트-맵 트라이)

  • 오승현;안종석
    • Journal of KIISE:Information Networking
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    • v.30 no.2
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    • pp.282-292
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    • 2003
  • This paper proposes an efficient data structure for forwarding IPv4 and IPv6 packets at the gigabit speed in backbone routers. The LPM(Longest Prefix Matching) search becomes a bottleneck of routers' performance since the LPM complexity grows in proportion to the forwarding table size and the address length. To speed up the forwarding process, this paper introduces a data structure named BMT(Bit-Map Tie) to minimize the frequent main memory accesses. All the necessary search computations in BMT are done over a small index table stored at cache. To build the small index table from the tie representation of the forwarding table, BMT represents a link pointer to the child node and a node pointer to the corresponding entry in the forwarding table with one bit respectively. To improve the poor performance of the conventional tries when their height becomes higher due to the increase of the address length, BMT adopts a binary search algorithm for determining the appropriate level of tries to start. The simulation experiments show that BMT compacts the IPv4 backbone routers' forwarding table into a small one less than 512-kbyte and achieves the average speed of 250ns/packet on Pentium II processors, which is almost the same performance as the fastest conventional lookup algorithms.

A Bloom Filter Application of Network Processor for High-Speed Filtering Buffer-Overflow Worm (버퍼 오버플로우 웜 고속 필터링을 위한 네트워크 프로세서의 Bloom Filter 활용)

  • Kim Ik-Kyun;Oh Jin-Tae;Jang Jong-Soo;Sohn Sung-Won;Han Ki-Jun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.7 s.349
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    • pp.93-103
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    • 2006
  • Network solutions for protecting against worm attacks that complement partial end system patch deployment is a pressing problem. In the content-based worm filtering, the challenges focus on the detection accuracy and its performance enhancement problem. We present a worm filter architecture using the bloom filter for deployment at high-speed transit points on the Internet, including firewalls and gateways. Content-based packet filtering at multi-gigabit line rates, in general, is a challenging problem due to the signature explosion problem that curtails performance. We show that for worm malware, in particular, buffer overflow worms which comprise a large segment of recent outbreaks, scalable -- accurate, cut-through, and extensible -- filtering performance is feasible. We demonstrate the efficacy of the design by implementing it on an Intel IXP network processor platform with gigabit interfaces. We benchmark the worm filter network appliance on a suite of current/past worms, showing multi-gigabit line speed filtering prowess with minimal footprint on end-to-end network performance.