• Korean Journal of Optics and Photonics
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• v.17 no.6
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• pp.564-568
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• 2006

Using the cross-gain modulation (XGM) characteristics of semiconductor optical amplifiers (SOAs), multi-functional all-optical logic gates, including XOR, AND, and OR gates are successfully simulated and demonstrated at 10Gbit/s. A VPI component maker^TM simulation tool is used for the simulation of multi-functional all-optical logic gates and the10 Cbit/s input signal is made by a mode-locked fiber ring laser. A multi-quantum well (MQW) SOA is used for the simulation and demonstration of the all-optical logic system. Our suggested system is composed of three MQW SOAs, SOA-1 and SOA-2 for XOR logic operation and SOA-2 and SOA-3 for AND logic operation. By the addition of two output signals XOR and AND, all-optical OR logic can be obtained.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.129-133
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• 2020

In this paper, a temperature compensation circuit is presented in order to mitigate gain variability due to temperature in the W-band low-noise amplifier (LNA). The proposed cascode temperature compensation bias circuit automatically controls gate bias voltages of the common-source LNA in order to suppress variations of small-signal gain. The designed circuit was realized in a 100-nm GaAs pHEMT process. The simulated voltage gain of W-band LNA including the proposed bias circuit is >20 dB with gain variability less than ±0.8 dB in the range of temperatures between -35 to 71℃. We expect that the proposed circuit contributes to millimeter-wave receivers for stable performances in radar applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1193-1200
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• 2005

In this paper, we proposed an image hiding method which decreases the amount of calculation encrypting partial data rather than the whole image data using a discrete wavelet transform and a linear scalar quantization which have been adopted as the main technique in JPEG2000 standard and then implemented the proposed algorithm to hardware. A chaotic system was used instead of encryption algorithms to reduce further amount of calculation. It uses a method of random changing method using the chaotic system of the data in a selected subband. For ciphering the quantization index it uses a novel image encryption algorithm of cyclical shifting to the right or left direction and encrypts two quantization assignment method (Top-down coding and Reflection coding), made change of data less. The experiments have been performed with the proposed methods implemented in software for about 500 images. The hardware encryption system was synthesized to find the gate-level circuit with the Samsung $0.35{\mu}m$ Phantom-cell library and timing simulation was performed, which resulted in the stable operation in the frequency above 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.5
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• pp.950-956
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• 2015

In this paper, a WiMedia Distributed-MAC (D-MAC) protocol is adopted for development of a seamless N-screen wireless service in Indoor and Ship Area Networks. Furthermore, to provide the OSMU (One Source Multi Use) N-screen service through P2P streaming in the seamless D-MAC protocol, a ATMT (Asynchronous Traffic Multi-hop Transmission) technology is proposed and analyzed. In this system, a WiMedia ATMT D-MAC bridge transmits control and managing information to various sensors and instruments, from a central integrated ship area network station. For this technology, a time slot allocation scheme for WiMedia asynchronous traffic and a multi-hop resource reservation scheme are combined to evaluate the performance of each scheme. From simulation results, the proposed ATMT scheme enhances performances in viewpoints of N-screen asynchronous data latency and throughput, compared to the conventional WiMedia D-MAC system.

• Korean Journal of Optics and Photonics
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• v.24 no.5
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• pp.262-270
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• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.613-619
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• 2003

Bluetooth is a communication technology enabling short-range devices to be wirelessly connected. A master and one or more slave devices are connected to form a piconet, and piconets are joined to form a scatternet. The units participating in two or more piconets in a scatternet, is called bridge or gateway nodes. In order to operate the scatternet efficiently, both piconet scheduling for the master and slaves of a piconet, and scatternet scheduling for the bridge nodes are playing important roles. In this paper, we propose a traffic-adaptive dynamic scatternet scheduling algorithm based on rendezvous points and rendezvous windows. The performance of the proposed algorithm is compared and analyzed with that of a static scheduling algorithm via simulations. Simulation results show that our algorithm can distribute wireless resources efficiently to bridge nodes depending on the traffic characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1A
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• pp.24-35
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• 2008

We propose a tree-based integrated network of infrastructure network and mobile ad hoc network to effectively support Mobile IP for mobile ad hoc networks and also proposed a network management protocol for formation and management of the integrated network and a tree-based routing protocol suitable for the integrated network. The integrated network has fixed gateways(IGs) that connect two hybrid networks and the mobile nodes in the network form a small sized trees based on the mobile nodes that are in the communication distance with a IG. A new node joins an arbitrary tree and is registered with its HA and FA along tree path. In addition, the proposed protocol establishes a route efficiently by using the tree information managed in every node. We examined the effectiveness of the tree-based integrated network for some possible network deployment scenarios and compared our routing protocol against the Mobile IP supported AODV protocol.