• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.30-32
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• 2000

내적을 계산하는데 있어서 Distributed Arithmetic(DA)을 사용하면 곱셈기를 사용하는 것보다 소비전력 및 크기를 효율적으로 줄일 수 있고, 고속동작이 가능한 회로구현이 쉽기 때문에 신호처리 시스템 설계에 많이 사용하고 있다. DA에는 롬-기반 DA와 가산기-기반 DA를 이용한 방법이 있는데, 가산기-기반 DA는 Sharing property와 계수의 Spare non-zero bit property를 최대한 이용하여 설계가 가능하기 때문에 크기 및 동작속도 측면에서 효율적인 구현이 가능하다. 본 논문에서는 가산기-기반 DA의 이러한 특성을 최대한 이용하여 멀티미디어 신호처리에 적합한 DCT/IDCT 프로세서를 설계하였고 다른 구조 및 롬-기반 DA와 비교 평가해본 결과 크기 및 속도 측면에서 효율적인 결과를 얻었다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.2
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• pp.1-5
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• 2002

Floating point unit system follows IEEE 754 Standard. In this paper, we used 1's complement system instead of 2's complement to practice the arithmetic. By converting we enable this system to compute simply and fast. To improve the speed of newly design adder, we used a transformation Carry selector adder of 53 bits. In paper, a design of floating point unit high efficiency micro processor system about for high speed. 

• Journal of Industrial Convergence
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• v.8 no.1
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• pp.49-64
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• 2010

Penalty tax of basic law that has been revised in December 30, 2006 has been amended to tax 40 percent on no report and under-reporting in unjustifiable way. This revision is a punitive regulation that reflects the national tax service's will to not sit back and watch taxpayers' intentional tax evasion by imposing a heavier tax burden, and it raised penalty tax rate that has been applied leniently compared to foreign countries. Therefore, this study examines how changes in penalty tax rate affected faithful tax report and in what level the punitive penalty tax rate should be legislated so that the effect of the penalty tax rate can be maximized by performing empirical analysis on the effect on income tax rate reporting standard of self-employed businesses before and after the time the penalty tax rate increased dramatically from 33.3% to 300% based on the items.

• The Mathematical Education
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• v.8 no.2
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• pp.19-20
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• 1970

이 논문에서는 거리공간 R가 가산적인 차원이 될 필요한 조건을 얻었으며 다음에는 거리공간 R가 가산개의 개집합에 의하여 덮어지고 각 개집합이 강한 귀납적 차원이 n 이하면 R의 강한 귀납적 차원도 n 이하이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• The Journal of Korean Association of Computer Education
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• v.16 no.3
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• pp.99-105
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• 2013

The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

• The Korean Journal of Applied Statistics
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• v.28 no.2
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• pp.231-239
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• 2015

A Poisson model is the first choice for counts data. Quasi Poisson or negative binomial models are usually used in cases of over (or under) dispersed data. However, these models might be unsuitable if the data consist of excessive number of zeros (zero inflated data). For zero inflated counts data, Zero Inflated Poisson (ZIP) or Zero Inflated Negative Binomial (ZINB) models are recommended to address the issue. In this paper, we further considered a situation where zero inflated data are spatially correlated. A mixed effect model with random effects that account for spatial autocorrelation is used to fit the data.

• 프린팅코리아
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• v.12 no.4
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• pp.78-81
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• 2013

세광제록스는 디지털인쇄 전문기업으로 웹프린팅서비스, 오프셋 마스터인쇄, 준공도 및 도서제작, 명함제작서비스, 디자인 등 다양한 서비스를 하고 있다. 세광제록스는 구로본점을 비롯해 가산지점, 동네북스, 서울역지점, 강남역지점, 용인신갈점(한국전력기술) 등을 운영하고 있다. 세광제록스 가산지점을 찾았다.

• Communications for Statistical Applications and Methods
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• v.3 no.1
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• pp.61-71
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• 1996

Kim and Song(1995)과 Kim and Lee(1996)는 하나의 이지공변량(binary covariate)을 갖는 가산위험모형(additive risk model)의 적합도검정법(goodness-of-fit test)을 제안했다. 전자는 모수의 가중추정량들의 차에 기초한 검정법이며 후자는 마팅게일잔차(martingale residual)에 기초한 검정법이다. 본 논문에서는 모의실험을 통하여 두 검정법을 비교하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.269-280
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• 1996

We proposed a symbolic substitution method based on an optical correlator for an optical parallel addition. In the proposed symbolic substitution method, we used redundant binary number of the symbolic substitution rules as a number system and chose MAC3E filter which had very low sidelobes and good correlation peak compared with SDF filter as the optical correlation filter. We encoeded input numbers property to increase the discrimination capability and divided inpt patterns into 5 groups of the same addition results to minimize the number of symbolic substitution rules. Through the computer simulation, we confirmed the proposed method was suitable to implement the optical parallel adder.