• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.11C
• /
• pp.1077-1084
• /
• 2006

This paper proposed a fast algorithm to reduce the amount of calculation for inter prediction which takes a great deal of the operational time in H.264/AVC. This algorithm decides a search range according to the direction of predicted motion vector, and then performs an adaptive spiral search for the candidates with JM(Joint Model) FME(Fast Motion Estimation) which employs the rate-distortion optimization(RDO) method. Simultaneously, it decides a threshold cost value for each of the variable block sizes and performs the motion estimation for the variable search ranges with the threshold. These activities reduce the great amount of the complexity in inter prediction encoding. Experimental results by applying the proposed method .to various video sequences showed that the process time was decreased up to 80% comparing to the previous prediction methods. The degradation of video quality was only from 0.05dB to 0.19dB and the compression ratio decreased as small as 0.58% in average. Therefore, we are sure that the proposed method is an efficient method for the fast inter prediction.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.5 no.1
• /
• pp.23-30
• /
• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.14 no.5
• /
• pp.81-86
• /
• 2014

A smart phone subscriber needs wide bandwidth services for more fast data communication on the internet. The conventional MIMO system is now developing to resolve these problems with limited device space for antenna and frequency band environment reserved. One of way to make it practically is to add the number of antennas theoretically. But it is difficult to increase the antenna element as a limited space on the system. Therefore an active beam forming scheme is known as a way of constructing a Compact MIMO system for that. In this paper, the fast switching control block was suggested to adjust a reactance of the antenna element and verified experimentally the effects by switching signal on an orthogonal beam forming through a spatial domain.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.38-47
• /
• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.48-54
• /
• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.5
• /
• pp.58-65
• /
• 2007

As multimedia portable devices become popular, the amount of computation for processing data including video compression has significantly increased. Various researches for low power consumption of the mobile devices and real time processing have been reported. Motion Estimation is responsible for 67% of H.264 encoder complexity. In this research, a new circuit is designed for motion estimation. The new circuit uses motion prediction based on approximate SAD, Alternative Row Scan (ARS), DAU, and FDVS algorithms. Our new method can reduce the amount of computation by 75% when compared to multi-frame motion estimation suggested in JM8.2. Furthermore, optimal number and size of reference frame blocks are determined to reduce computation without affecting the PSNR. The proposed Motion Estimation method has been verified by using the hardware and software Co-Simulation with iPROVE. It can process 30 CIF frames/sec at 50MHz.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.10C
• /
• pp.820-828
• /
• 2008

In order to achieve high coding efficiency, H.264/AVC video coding standard adopts the techniques such as variable block size coding, motion estimation with quarter-pel precision, multiple reference frames, rate-distortion optimization, and etc. However, these coding methods have a defect to greatly increase the complexity for motion estimation. Particularly, from multiple reference frame motion estimation, the computational burden increases in proportion to the number of the searched reference frames. Therefore, we propose the method to reduce the complexity by controlling the number of the searched reference frames in motion estimation. Proposed algorithm uses the optimal reference frame information in both $P16{\times}16$ mode and the adjacent blocks, thus omits unnecessary searching process in the rest of inter modes. Experimental results show the proposed method can save an average of 57.31% of the coding time with negligible quality and bit-rate difference. This method also can be adopted with any of the existing motion estimation algorithm. Therefore, additional performance improvement can be obtained.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.38 no.3
• /
• pp.282-291
• /
• 2001

In this paper, an efficient VLSI architecture of Shape Adaptive Discrete Cosine Transform(SADCT) based on systolic array is proposed. Since transform size in SADCT is varied according to the shape of object in each block, it are dropped that both usability of processing elements(PE´s) and throughput rate in time-recursive SADCT structure. To overcome these disadvantages, it is proposed that the architecture based on a systolic way structure which doesn´t need memory. In the proposed architecture, throughput rate is improved by consecutive processing of one-dimensional SADCT without memory and PE´s in the first column are connected to that in the last one for improvement of usability of PE. And input data are put into each column of PE in parallel according to the maximum data number in each rearranged block. The proposed architecture is described by VHDL. Also, its function is evaluated by MentorTM. Even though the hardware complexity is somewhat increased, the throughput rate is improved about twofold.

• KIPS Transactions on Computer and Communication Systems
• /
• v.5 no.2
• /
• pp.33-40
• /
• 2016

Due to the growth of social network systems (SNS), big data are realized and Hadoop was developed as a distributed platform for analyzing big data. Enterprises analyze data containing users' sensitive information by using Hadoop and utilize them for marketing. Therefore, researches on data encryption have been done to protect the leakage of sensitive data stored in Hadoop. However, the existing researches support only the AES encryption algorithm, the international standard of data encryption. Meanwhile, Korean government choose ARIA algorithm as a standard data encryption one. In this paper, we propose a HDFS data encryption scheme using ARIA algorithms on Hadoop. First, the proposed scheme provide a HDFS block splitting component which performs ARIA encryption and decryption under the distributed computing environment of Hadoop. Second, the proposed scheme also provide a variable-length data processing component which performs encryption and decryption by adding dummy data, in case when the last block of data does not contains 128 bit data. Finally, we show from performance analysis that our proposed scheme can be effectively used for both text string processing applications and science data analysis applications.

• 전자공학회논문지 IE
• /
• v.43 no.4
• /
• pp.37-42
• /
• 2006

This paper proposes a adaptive video watermarking algorithm according to bitrate and motion vector size in MPEG2 system. The watermark strength in the I-frames is adapted for quantization step size and the strength in the P-B-frames is adapted for quantization step size and motion vector of macroblock to make the watermark more robust against the accompanying degradation due to aggressively compression. A realtime watermark extraction is done directly in the DCT domain during MPEG decoding without full decoding of MPEG video. The experimental simulations show that the video quality results almost invisible difference between the watermarked frames and the original frames and the watermark is resistant to frame dropping, MPEG compression, GoP conversion and low pass filter attacks.