• 제목/요약/키워드: 가변구조제어

검색결과 418건 처리시간 0.024초

Efficient Harmonic-CELP Based Low Bit Rate Speech Coder (효율적인 하모닉-CELP 구조를 갖는 저 전송률 음성 부호화기)

  • 최용수;김경민;윤대희
    • The Journal of the Acoustical Society of Korea
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    • 제20권5호
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    • pp.35-47
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    • 2001
  • This paper describes an efficient harmonic-CELP speech coder by taking advantages of harmonic and CELP coders into account. According to frame voicing decision, the proposed harmonic-CELP coder adopts the RP-VSELP coder as a fast CELP in case of an unvoiced frame, or an improved harmonic coder in case of a voiced frame. The proposed coder has main features as follows: simple pitch detection, fast harmonic estimation, variable dimension harmonic vector quantization, perceptual weighting reflecting frequency resolution, fast harmonic synthesis, naturalness control using band voicing, and multi-mode. These features make the proposed coder require very low complexity, compared with HVXC coder To demonstrate the performance of the proposed coder, a 2.4 kbps coder has been implemented and compared with reference coders. From results of informal listening tests, the proposed coder showed good quality while requiring low delay and complexity.

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The copy networks controlling the copy number according to the fluctuations of the input traffics for an ATM Multicast Switch (입력 트래픽의 특성에 따라 복사 수가 제어되는 ATM 멀티캐스트 스위치 복사 망)

  • Paik, Jung-Hoon;Lim, Chae-Tak
    • Journal of the Korean Institute of Telematics and Electronics S
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    • 제35S권10호
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    • pp.52-63
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    • 1998
  • In this paper, several improvements to a copy network proposed previously for multicast packet switching are described. The improvements provide a solution to some problems inherent in multicasting. The input fairness problem caused by overf low is solved by a dynamic starting point decider(DSD), which can calculate running sums of copy requests starting from any input port. The starting point is changed adaptively in every time slot based on both the fill level of the input buffers in current time slot and the overflow situations of the previous time slot. Using the fill level of the conventional network. The DSD also provides the function of regulating overall copy requests according to the amount of input traffics. This is an essential function in improving overall throughputs of the copy networks. The throughput of a multicast switch can be improved substantially if partial service of copy request is implemented when overflow occurs. Call-splitting can also be implemented by the DSD in a straightforward manner. The hardware for the DSD is derived with the objective of simple architectures for the high speed operation. Simulation study of the copy network under various traffic conditions is presented to evaluate its performance.

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An Improved Continuous Integral Variable Structure Systems with Prescribed Control Performance for Regulation Controls of Uncertain General Linear Systems (불확실 일반 선형 시스템의 레귤레이션 제어를 위한 사전 제어 성능을 갖는 개선된 연속 적분 가변구조 시스템)

  • Lee, Jung-Hoon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • 제66권12호
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    • pp.1759-1771
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    • 2017
  • In this paper, an improved continuous integral variable structure systems(ICIVSS) with the prescribed control performance is designed for simple regulation controls of uncertain general linear systems. An integral sliding surface with an integral state having a special initial condition is adopted for removing the reaching phase and predetermining the ideal sliding trajectory from a given initial state to the origin in the state space. The ideal sliding dynamics of the integral sliding surface is analytically obtained and the solution of the ideal sliding dynamics can predetermine the ideal sliding trajectory(integral sliding surface) from the given initial state to the origin. Provided that the value of the integral sliding surface is bounded by certain value by means of the continuous input, the norm of the state error to the ideal sliding trajectory is analyzed and obtained in Theorem 1. A corresponding discontinuous control input with the exponential stability is proposed to generate the perfect sliding mode on the every point of the pre-selected sliding surface. For practical applications, the discontinuity of the VSS control input is approximated to be continuous based on the proposed modified fixed boundary layer method. The bounded stability by the continuous input is investigated in Theorem 3. With combining the results of Theorem 1 and Theorem 3, as the prescribed control performance, the pre specification on the error to the ideal sliding trajectory is possible by means of the boundary layer continuous input with the integral sliding surface. The suggested algorithm with the continuous input can provide the effective method to increase the control accuracy within the boundary layer by means of the increase of the $G_1$ gain. Through an illustrative design example and simulation study, the usefulness of the main results is verified.

Miniaturized Hairpin Tunable Filter with the Single Control Voltage (단일 제어 전원을 갖는 소형화된 헤어핀 튠어블 필터)

  • Myoung, Seong-Sik;Hong, Young-Pyo;Jang, Byung-Jun;Lee, Yong-Shik;Yook, Jong-Gwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • 제18권10호
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    • pp.1126-1135
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    • 2007
  • This paper presents the varactor-tuned miniaturized hairpin tunable filter with a single control voltage. The previously proposed miniaturization method is a very straight-forward method to miniaturize a parallel coupled-line filter. In this paper, the miniaturized hairpin tunable filter is proposed with the constant ratio rule of that the capacitances of the each stage always have constant ratio without any dependency to miniaturized electrical length. To show the validity of the proposed method, a 3rd order 0.5 dB ripple Chebyshev fitter with a center frequency of 900 MHz and a fractional bandwidth(FBW) of 10 % was designed and fabricated. The fabricated filter was based on CER-10 substrate of Taconic Inc. with 1SV277 varactor diode of Toshiba Inc. The center frequency of the fabricated filter can be changed from 606 MHz to 944 MHz, 338 MHz with the control voltage from 0.5 V to 4 V. The insertion loss of the proposed filter is increased with the increment of the control voltage, and the filter characteristics are well reserved expect of slight change of the bandwidth with the various control voltage.

Optical true time-delays for phased-array antennas using 2×2 MEMS switches and fiber delay lin (2×2 MEMS 스위치와 광섬유 지연선로를 이용한 위상배열 안테나용 실시간 지연선로)

  • Lee, Gab-Yong;Choi, Yeon-Bong;Shin, Jong-Dug;Kim, Boo-Gyoun
    • Korean Journal of Optics and Photonics
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    • 제13권4호
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    • pp.289-294
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    • 2002
  • We propose optical true time-delays (TTDs) for phased-array antennas (PAAs) composed of 2${\times}$2 MEMS switches and fiber delay lines, and implement a TTD which shows a maximum scan angle of $120^{o}$ with $30^{o}$ resolution. Since this structure uses only one fixed wavelength laser diode, it provides several advantages such as easy control, high speed operation, and low cost compared with those of the optical TTDs using tunable laser sources. We design a four element linear PAA using the proposed TTDs at 10 ㎓. Simulation results show that the maximum gain is 11.6 dB at the radiation angle $0^{o}$, 11.2 dB at $\pm$$30^{o}$, and 10.6 dB at $\pm$$60^{o}$.

Attenuator using Lossy Left-Handed Transmission Line and Vector Modulator Application (손실이 있는 Left-Handed 전송선로를 이용한 감쇠기와 벡터 변조기 응용)

  • Kim, Seung-Hwan;Kim, Ell-Kou;Kim, Young;Yoon, Young-Chul
    • Journal of Advanced Navigation Technology
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    • 제13권3호
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    • pp.399-405
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    • 2009
  • This paper proposes a design of attenuator based on meta-material structure and its application. The unit-cell attenuator based on the lossy transmission line consists of the CRLH(Composite Right/Left Handed) transmission line and PIN diodes to be controlled internal loss according to diode bias voltage to change resistance of diode. Also, to reduce the initial losses, there is used parallel connection of PIN diodes. To increase attenuations, it is connected a cascade unit-cell of attenuator with periodic structure. The attenuation quantities of unit-cell are about 10dB and phase variations are 15o maximum at 1.5 GHz ~ 2.5 GHz. Also, its application is represented a vector modulator.

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Design of IIR Structure Active Mufflers using Stabilized Filter Algorithms (안정화 필터 알고리즘을 적용한 IIR 구조 능동 머플러의 설계)

  • Ahn, Dong-Jun;Nam, Hyun-Do
    • Journal of the Korea Academia-Industrial cooperation Society
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    • 제20권3호
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    • pp.570-575
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    • 2019
  • Active muffler is implemented by applying active noise control technique to reduce exhaust noise of automobile muffler. Conventional Filtered_x LMS algorithm has a problem that the degree of control filter becomes very large and convergence deteriorates when acoustic feedback is present. The recursive LMS algorithm can compensate for this problem because it can be easily diverted in the adaptive filter adaptation process. In this paper, the structure of the primary path and the secondary path transfer function is designed as the IIR filter to improve the convergence performance and the computational burden, and the stabilization filter algorithm is applied to secure stability which is a disadvantage of the IIR filter structure. The stabilization filter algorithm plays a role of pulling the pole into the unit circle to prevent the pole of the transfer function corresponding to the acoustic feedback from diverging during the adaptation process. In this way, the computational burden of the active muffler system and the convergence performance can be improved. In order to show the usefulness of the proposed system, we compared the performance of the proposed Filtered_x LMS algorithm with the performance of the proposed system for the exhaust sound of a diesel engine, which is a variable environment. Compared to conventional algorithm, proposed algorithm's computational burden is less than half, and convergence performances are more than 4 times.

Transfer System using Radial Electrodynamic Wheel over Conductive Track (래디얼 동전기 휠을 이용한 전도성 트랙 위에서의 이송 시스템)

  • Jung, Kwang Suk
    • Journal of the Korea Academia-Industrial cooperation Society
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    • 제18권11호
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    • pp.794-801
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    • 2017
  • When a radial wheel is placed so as to partially overlap a conductive plate and rotated, a lift force is generated on the wheel, a thrust force along the edge, and a lateral force which tends to reduce the overlap region. When several of these wheels are combined, it is possible to realize a system in which the stability of the remaining axes is ensured, except in the traveling direction. To validate the overall characteristics of the multi-wheel system, we propose a transfer system levitated magnetically using radial electrodynamic wheels. The proposed system is floated and propelled by four wheels and arranged in a structure that allows the thrusts generated by the front and rear wheels to offset each other. The dynamic stability of the wheel and the effect of the pole number on the three-axial forces are analyzed by the finite element method. At this time, the thrust and levitation force are strongly coupled, and the only factor affecting them is the wheel rotation speed. Therefore, in order to control these two forces independently, we make use of the fact that the ratio of the thrust to the levitation force is proportional to the velocity and is independent of the size of the gap. The in-plane and out-of-plane motion control of the system is achieved by this control method and compared with the simulation results. The experimental results show that the coupled degrees of freedom can be effectively controlled by the wheel speed alone.

Analysis of Hydraulic Characteristics According to Operation of Movable Weir (가동보 운영에 따른 수리학적 특성 분석)

  • Seo, Il Won;Park, Sung Won;Kim, Tae-Won
    • 한국방재학회:학술대회논문집
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    • 한국방재학회 2011년도 정기 학술발표대회
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    • pp.101-101
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    • 2011
  • 현재 국내에서 시행되고 있는 '4대강 살리기 사업'은 하천에서 발생하는 홍수 및 가뭄재해방지를 위한 다양한 공학적 노력을 시도하고 있다. 특히 안정적인 수위 및 유량확보와 홍수방지를 위한 보(weir)가 4대강 유역에 16개 설치되고 있다. 이러한 보 구간에는 고정보와 가동보가 복합적으로 설치되고 있으며 가동보는 그 형상과 운영방식에 따라 다양한 설계방안이 적용되었다. '4대강 살리기 사업' 중 낙동강 23공구의 강정보 공사 구간에는 원호형태의 측면 형상을 갖는 라이징 섹터게이트(Rising sector gate)가 적용되었다. 라이징 섹터게이트는 구조물의 높이가 낮고 수문의 개폐장치가 수문피어 구조물 내에 설치되어 경관이 우수하며, 구조가 간단하여 비체와 수류의 안정성이 뛰어나기 때문에 4개의 공사구간에 적용되었다. 따라서 본 연구에서는 강정보의 가동보 구간 2문 중 1문을 1/100 축척으로 제작하여 가변경사 개수로에 설치하고, 홍수 빈도별 상류 유량 조건과 하류단 수위조건으로 케이스를 정하여 실험을 수행하였다. 본 실험에서 사용한 개수로 장치는 너비 0.6 m, 높이 0.8 m, 그리고 길이 15.0 m(측정가능 구간, 헤드탱크와 테일게이트 부제외)의 개수로 실험장치이다. 측부는 모두 강화유리로 되어 육안관찰 및 계측 시 용이하게 제작되었으며, 순환식 유량 공급장치를 구축하여 수로의 하부에 설치된 유량탱크로부터 계속적으로 순환하도록 설계되었다. 또한 수로 하단으로부터 상단방향으로 약 33 m 지점에 전동 유압식 Jack screw 2기가 설치되어 경사도를 조절할 수 있도록 제작되었다. 유량조절용 판넬의 제어기판에는 디지털 경사계가 설치되어 있기 때문에 보다 정확한 경사도의 조절이 가능하다. 보 모형의 총연장은 53 cm이며 폭은 45 cm이다. 섹터게이트의 게이트부분은 직경 15 cm로 설계하였다. 문주부분을 포함한 모든 모형은 아크릴로 제작하며 레이저의 주사를 방해하지 않으며 투과율을 최대로 할 수 있도록 고강도의 아크릴을 가장 얇게 하여 중공형태를 채택하였다. 실험조건은 우선 보의 운영방안에 따라 게이트의 4가지 개방도를 설정하였고, 특히 평수위조건에서는 보의 상류부에 퇴적된 퇴적물의 세척을 위한 flushing 운영개방도 포함되어 있다. 홍수시에 대한 유량조건은 2년 빈도에 해당하는 유량을 수문의 비율과 상사법칙에 따라 설정하였으며 하류단 수위조건도 동일한 조건에 대한 값을 채택하여 적용하였다. 유동장의 해석을 위해서는 비접촉식 계측방법인 PIV(Particle Image Velocimetry) 시스템을 채택하여 2차원(x-z 방향) laser sheet를 생성하고 주입된 particle에서 반사된 변위(displacement) 정보를 상호상관(cross-correlation)기법으로 유동장을 계산하였다. 또한 수리모형과 동일한 지형격자를 구축하여 3차원 CFD 프로그램인 FLOW-3D로 계산하여 결과를 비교하였다. 특히 flushing 운영방안에 대한 게이트부의 개방도를 세가지(30, 45, $60^{\circ}$)로 구분하여 모의하였고, 적절한 개방도를 제안하고자 하였다. 실험결과는 우선 4가지 운영방안에 대한 가동보 주변에서의 유속장을 파악하였고, 최대유속의 발생위치의 변화를 확인할 수 있었다. 그리고 이에 따른 보의 바닥에서 최대유속이 발생할 경우, 하상보호공 위치와 거리 등에 대해서 분석하였다. 이를 통해 가동보 운영에 따른 다양한 유속구조를 파악할 수 있게 되며 구조적 안정성 확보를 위한 검증자료로 활용될 수 있을 것으로 예상된다. 향후, 가동보 운영방안 중 수세효과(flushing effect)에 대한 효과분석을 위해 게이트부 상류구간에 적절한 입경과 비중의 퇴적물질을 설치하는 연구와 상류부에서의 유입유사농도 및 시간변화에 따른 퇴적에 관한 연구를 수행할 계획이다.

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A VLSI Design of High Performance H.264 CAVLC Decoder Using Pipeline Stage Optimization (파이프라인 최적화를 통한 고성능 H.264 CAVLC 복호기의 VLSI 설계)

  • Lee, Byung-Yup;Ryoo, Kwang-Ki
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제46권12호
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    • pp.50-57
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    • 2009
  • This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.