• Title/Summary/Keyword: (Bi,La)${Ti_3}{O_{12}}$

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Ferroelectric properties of BLT films deposited on $ZrO_2$Si substrates

  • Park, Jun-Seo;Lee, Gwang-Geun;Park, Kwang-Hun;Jeon, Ho-Seung;Im, Jong-Hyun;Park, Byung-Eun;Kim, Chul-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.172-173
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    • 2006
  • Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.

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Fabrication and Characterization of the BLT/STA/Si Structure for Fe-FETs Application

  • Park, Kwang-Huna;Jeon, Ho-Seung;Park, Jun-Seo;Im, Jong-Hyun;Park, Byung-Eun;Kim, Chul-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.73-74
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    • 2006
  • Ferroelectric thin films have been widely investigated for future nonvolatile memory application. We fabricated the BLT ($(Bi,La)_4Ti_3O_{12}$) films on Si using a STA ($SrTa_2O_6$) buffer layer BLT and STA film were prepared by sol-gel method. Measurement data by XRD and AFM, showed that BLT film and STA films were well crystallized and a good surface morphology. From C-V measurement reward that the Au/BLT/STA/Si structure showed a clockwise hysteresis loop with a memory window of 1.5 V for the bias voltage sweep of ${\pm}5$ V. From results, the Au/BLT/STA/Si structure is useful for FeFETs.

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The Mineralogical and Geochemical Study on Korean Scheelites and its Application to the Ore Prospecting (한국산 灰重石鑛의 광물학적, 지화학적 연구 및 그의 探査에의 이용)

  • So, Chil-Sup;Park, Maeng-Eon
    • Economic and Environmental Geology
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    • v.12 no.2
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    • pp.79-93
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    • 1979
  • Twenty five samples of the scheelite-powellite series from twelve Korean tungsten deposits of various geologic settings were studied mineralogically and geochemically. Variations in the trace-element contents of the scheelite minerals are considered in relation to geologic settings and mineralogic properties. Scheelites from ore deposits developed in similar geologic settings and under similar physicochemical conditions are characterized by specific combinations of trace elements.

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Degradation from Polishing Damage in Ferroelectric Characteristics of BLT Capacitor Fabricated by Chemical Mechanical Polishing Process (화학적기계적연마 공정으로 제조한 BLT Capacitor의 Polishing Damage에 의한 강유전 특성 열화)

  • Na, Han-Yong;Park, Ju-Sun;Jung, Pan-Gum;Ko, Pil-Ju;Kim, Nam-Hoon;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.236-236
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    • 2008
  • (Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

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