• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.29-34
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• 2009

PLZT thin films were deposited on platinized silicon (Pt/$TiSiO_2$/Si) substrate by RF magnetron sputtering. A $TiO_2$ buffer layer was fabricated, prior to deposition of PLZT films. the layer was strongly affected the crystallographic orientation of the PLZT films. X-ray diffraction was performed on the films to study the crystallization of the films as various substrate temperatures (Ts). According to increasing Ts, preferred orientation of films was changed (110) plane to (111) plane. The ferroelectric, dielectric and electrical properties of the films were also investigated in detail as increased substrate temperatures. The PLZT films deposited at $400^{\circ}C$ showed good ferroelectric properties with the remnant polarization of $15.8{\mu}C/cm^2$ and leakage current of $5.4{\times}10^{-9}\;A/cm^2$.

• 한국세라믹학회지
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• 제42권12호
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• pp.787-792
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• 2005

A symmetrical LSCF $(La_{0.6}Sr_{0.4}Co_{0.2}Fe_{0.8}O_{3-\delta})\;ScSZ(89ZrO_2-10Sc_2O_3-1CeO_2)/LSCF$ electrochemical cell with a GDC (Gadolinium-Doped Ceria, $90CeO_2-10Gd_2O_3$) interlayer that was inserted between the LSCF cathode and ScSZ electrolyte was fabricated, and the electrochemical performance of these cells was evaluated. The GDC interlayer was deposited on a ScSZ electrolyte using a screen-printing technique. The GDC interlayer prevented the unfavorable solid-state reactions at the LSCF/ScSZ interfaces. The LSCF cathode on the GDC interlayer had excellent electrocatalytic performance even at $650^{\circ}C$. The Area Specific Resistance (ASR) was strongly dependent on the thickness and heat-treatment temperature of the GDC interlayer. The impedance spectra showed that the cell with a $15\~27{\mu}m$ thick GDC interlayer heat-treated at $1200^{\circ}C$ had the lowest ASR.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• 한국재료학회지
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• 제8권12호
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• pp.1170-1175
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• 1998

하부전극 없이 MgO 중간층을 갖는 고농도로 도핑된 Si(100) 기판(MgO/Si)위에 고주파 마그네트론 스퍼터링 방법으로 as-deposited PZT 박막을 증착한후 $650^{\circ}C$ 온도에서 RTA 후속열처리를 실시하였다. 제작된 PZT 박막시료에 대해 MgO 중간층의 두께 및 후속열처리에 따른 결정학적, 전기적특성을 조사하였다. XRD 분석결과 MgO층이 전혀 증착되지 않은 bare Si 기판위에 증착된 PZT 시료는 pyrochlore 결정상만이 나타났으나 50 두께의 M gO층 위에 증착된 PZT/MgO/Si 박막시료는 전형적인 perovskite 결정구조를 나타내었다. SEM 및 AES 분석결과 PZT 박막두게는 약 7000 이었으며 비교적 매끄러운 계면형상을 보여 주었다. PZT 박막내의 각 성분원소가 깊이에 따라 비교적 균일한 분포를 나타내었다. $650^{\circ}C$의 온도로 후속열처리된 PZT/MgO/Si 박막의 1KHz 주파수에서 유전상수 ($\varepsilon_{r}$ )와 잔류분극 (2Pr)은 약 300 및 $14\mu$C/$\textrm{cm}^2$의 값을 각각 나타내었으며 누설전류의 크기는 약 $3.2\mu$A/$\textrm{cm}^2$이었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.66-79
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• 2008

Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides ($Nb_2O_5$, and $ZrO_x$) and subsequently the resistive switching of $Cu_xO$ and heavily Cu-doped $MoO_x$ film for their compatibility with modem transistor-process cycles. Single-crystalline Nb-doped $SrTiO_3$ (NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.