• Korean Journal of Materials Research
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• v.3 no.3
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• pp.310-315
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• 1993

The effects of RT A treatment on the breakdown strengths were studied for tantalum pentoxide(${Ta_2}{O_5}$) films prepared by thermal oxidation of dc-sputtered Ta(400$\AA$) on p-type (100) Si wafer. While the relative dielectric constants of the RT A -treated specimens were not remarkably affected, the breakdown strengths of the RTA-treated specimens were greatly changed by RTA temperature and time. After the RTA treatment, the breakdown strengths of the specimens RTA-treated at the temperature below the crystallization temperature were increased to 5.4MV /cm, while those of the specimens RTA -treated at the temperature above it were decreased to 0.5MV /cm. RTA time-independence of the flat-bant voltage shift refleted that the RT A post-annealing effects on the breakdown strengths were not due to the interface reaction between the ${Ta_2}{O_5}$ layer and the Si substrate but, through the RBS analysis, to densification of the ${Ta_2}{O_5}$ films.

• Proceedings of the Materials Research Society of Korea Conference
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• 2000.11a
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• pp.80-80
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• 2000

차세대 대화면 평판 디스플레이에서 가장 주목을 받고 있는 디스플레이 소자는 PDP라고 할 수 있다. PDP 패널 제조 공정 기술에서 난해한 공정 중 하나인 투명 유전체 제조 공정은 현재까지 인쇄법에 의한 연구가 주로 진행되어 왔다. 그러나 인쇄법은 여러 번의 인쇄와 건조, 소성이 반복되어야 함으로써 유전체 제조에 있어서 복잡한 제조 공정이므로 대폭 단순화할 필요가 있다. 이에 대한 해결책으로서 제시된 것이 tape casting을 이용한 건식 공정이다. 본 연구에서는 tape casting용 slurry에 포함되는 유기물인 binder, plasticizer, solvent의 변화에 따른 dry film의 특성 및 소성 조건에 따른 유전체 특성에 관하여 조사하였다. PbO-SiO$_2$-B$_2$O$_3$계 유리 분말과 유기 vehicle을 ball mill을 이용하여 분산, 혼합하여 tape casting용 slurry를 제조하고, 이 slurry를 doctor blade법으로 tape를 제조하고 건조한 후 유리기판에 transfer한 후 소성하였다. Slurry의 조건과 소성 조건에 따른 투광성, 표면 조도 및 단면의 미세구조 등 투명 유전체의 특성을 평가하였다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.29-32
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• 2000

Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO$_{3}$/AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$.cmcm

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.71-74
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• 1998

In this Paper, we investigate the electrical properties of ultra-thin(70${\AA}$) nitrided(NO) and reoxidized nitrided oxide(ONO) film that ale considered to be premising candidates for replacing conventional silicon dioxide film in ULSI level integration. we studied I$\sub$g/-V$\sub$g/ characteristics to know the effect of nitridation and reoxidation on the current conduction, leakage current time-dependent dielectric breakdown(TDDB) to evaluate charge-to-breakdown(Q$\sub$bd/), and the effect of stress temperature(25, 50, 75, 100$^{\circ}C$) and compared to those with thermal gate oxide(SiO$_2$) of identical thickness. From the measurement results, we find that reoxidized nitrided oxide(ONO) film shows superior dielectric characteristics, leakage current, and breakdown-to-charge(Qbd) performance over the NO film, while maintaining a similar electric field dependence compared to NO layer. Besides, ONO film has strong resistance against variation in temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1122-1127
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• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Korean Journal of Materials Research
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• v.4 no.4
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• pp.453-458
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• 1994

$(Ba_{0.5}Sr_{0.5)/TiO_3$(BST) thin films were prepared for the application of 256 Mb DRAM by RF magnetron sputtering. The crystallinity of BST thin films increased with increasing deposition tempera lure. The composition of thin films was $(Ba_{0.48}Sr_{0.48)/TiO_{2.93}$ Pt/Ti barrier layer suppressed the diffusion of Si into BST layer. The films showed a dielectric constant of 320 and a dissipation factor of 0.022 at 100 kHz. the change of capacitance of the films with applied voltage was small, showing paraelectric property. The charge storage density and leakage current density were 40fC/$\mu \textrm{m}^{2}$ and 0.8$\mu A/\textrm{cm}^2$, respectively at a field of 0.15 MV/cm. The BST films obtained by RF magnetron sputtering appeared to be potential thin film capacitors for 256 Mb DRAM application.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.129-129
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• 2016

Graphene, as a single layer of $sp^2$-bonded carbon atoms packed into a 2D honeycomb crystal lattice, has attracted much attention due to its outstanding properties. In order to synthesize high quality graphene, transition metals, such as nickel and copper, have been widely employed as catalysts, which needs transfer to desired substrates for various applications. However, the transfer steps are not only complicated but also inevitably induce defects, impurities, wrinkles, and cracks of graphene. Furthermore, the direct synthesis of graphene on dielectric surfaces has still been a premature field for practical applications. Therefore, cost effective and concise methods for transfer-free graphene are essentially required for commercialization. Here, we report a facile transfer-free graphene synthesis method through nickel and carbon co-deposited layer. In order to fabricate 100 nm thick NiC layer on the top of $SiO_2/Si$ substrates, DC reactive magnetron sputtering was performed at a gas pressure of 2 mTorr with various Ar : $CH_4$ gas flow ratio and the 200 W DC input power was applied to a Ni target at room temperature. Then, the sample was annealed under 200 sccm Ar flow and pressure of 1 Torr at $1000^{\circ}C$ for 4 min employing a rapid thermal annealing (RTA) equipment. During the RTA process, the carbon atoms diffused through the NiC layer and deposited on both sides of the NiC layer to form graphene upon cooling. The remained NiC layer was removed by using a 0.5 M $FeCl_3$ aqueous solution, and graphene was then directly obtained on $SiO_2/Si$ without any transfer process. In order to confirm the quality of resulted graphene layer, Raman spectroscopy was implemented. Raman mapping revealed that the resulted graphene was at high quality with low degree of $sp^3$-type structural defects. Additionally, sheet resistance and transmittance of the produced graphene were analyzed by a four-point probe method and UV-vis spectroscopy, respectively. This facile non-transfer process would consequently facilitate the future graphene research and industrial applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.734-737
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• 2004

The metal-ferroelectric-semiconductor (MFS) structure is widely studied for nondestructive readout (NDRO) memory devices, but conventional MFS structure has a critical problem. It is difficult to obtain ferroelectric films like PZT on Si substrate without interdiffusion of impurities such as Pb, Ti and other elements. In order to solve these problems, the metal-ferroelectric-insulator-semiconductor (MFIS) structure has been proposed with a buffer layer of high dielectric constant such as MgO, $Y_2O_3$, and $CeO_2$. In this study, the etching characteristics (etch rate, selectivity) of MgO thin films were etched using $Cl_2/Ar$ plasma. The maximum etch rate of 85 nm/min for MgO thin films was obtained at $Cl_2$(30%)/Ar(70%) gas mixing ratio. Also, the etch rate was measured by varying the etching parameters such as ICP rf power, dc-bias voltage, and chamber pressure. Plasma diagnostics was performed by Langmuir probe (LP) and optical emission spectroscopy (OES).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.19-19
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• 2007

Excimer laser annealing (ELA) 방법을 이용하여 결정화하고 게이트 절연체로써 high-k 물질을 가지는 다결정 실리콘박막 트랜지스터의 전기적 특성을 평가하였다. 다결정 실리콘 박막 트랜지스터는 비결정질 실리콘 박막 트랜지스터 보다 높은 전계 효과 이동도와 운전 용이한 장점을 가진다. 기존의 결정화 방법으로는 다결정 실리콘 박막 트랜지스터의 높은 열 공급을 피할 수 없기 때문에, 매몰 산화막 위의 비결정질 박막은 저온에서 다결정 실리콘 결정화를 위해 KrF excimer laser (248nm)를 이용하여 가열 냉각 공정을 했다. 게다가 케이트 절연체로써 atomic layer deposition (ALD) 방법에 의해 저온에서 20 nm의 고 유전율을 가지는 $HfO_2$ 박막을 증착하였다. 알루미늄은 n-MOS 박막 트랜지스터의 게이트 전극으로 사용되었다. 금속 케이트 전극을 사용하여 게이트 공핍 효과와 관계되는 케이트 절연막 두께의 증가를 예방할 수 있고, 게이트 저항의 감소에 의해 소자 속도를 증가 시킬 수 있다. 추가적으로, 비결정질 실리콘 박막의 결정화 기술로써 사용된 ELA 방법은 SPC (solid phase crystallization) 방법과 SLS (sequential lateral solidification) 방법에 의해 비교되었다. 결과적으로, ELA 방법에 의해 결정화된 다결정 실리콘 박막의 결정도와 표면 거칠기는 SPC와 SLS 방법에 비해 개선되었다. 또한, 우리는 ELA 결정화 방법에 의한 다결정 실리콘 박막 트랜지스터로부터 우수한 소자 특성을 얻었다.