• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• 전기전자학회논문지
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• 제27권1호
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• pp.19-24
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• 2023

약 1.12 ev의 밴드갭 에너지를 갖는 실리콘은 동작 온도가 250 ℃ 이하로 제한되어, 밴드갭 에너지가 큰 SiC 기판을 이용한 MIS(metal-insulator-semiconductor) 구조의 시료를 제작하여 고온에서 수소 응답 특성을 고찰하였다. 적용된 유전체 박막은 수소가스에 대해 침투성이 강하고 고온에서 안정성을 보이는 탄탈륨 산화막(Ta₂O₅)으로, 스퍼터링으로 증착된 탄탈륨(Ta)을 900 ℃의 온도에서 급속열산화법(RTO)으로 형성하였다. 이렇게 형성된 탄탈륨 산화막은 TEM, SIMS, 및 누설전류 측정을 통해, 두께, 원소들의 깊이 분포 및 절연특성을 분석하였다. 수소가스 응답특성은 0부터 2,000 ppm의 수소가스 농도에 대해, 상온으로부터 200와 400 ℃의 온도에서 정전용량의 변화로 평가하였다. 그 결과, 시료로부터 감도가 우수하고, 약 60초의 응답 시간을 나타내는 특성을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.303.2-303.2
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• 2014

The oxides of group IV transition metals such as titanium, zirconium, hafnium have many important current and future application, including protective coatings, sensors and dielectric layers in thin film electroluminescent (TFEL) devices. Recently, group IV transition metal oxide films have been intensively investigated as replacements for SiO2. Due to high permittivities (k~14-25) compared with SiO2 (k~3.9), large band-gaps, large band offsets and high thermodynamic stability on silicon. Herein, we report the synthesis of new group IV transition metal complexes as useful precursors to deposit their oxide thin films using chemical vapor deposition technique. The complexes were characterized by FT-IR, 1H NMR, 13C NMR and thermogravimetric analysis (TGA). Newly synthesised compounds show high volatility and thermal stability, so we are trying to deposit metal oxide thin films using the complexes by Atomic Layer Deposition (ALD).

• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1638-1643
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• 2018

Multi-layer ceramic capacitors as decoupling capacitor were fabricated by dielectric composition with a high dielectric constant. The fabricated decoupling capacitors were embedded in the PCB of the 10G RF transceiver module and evaluated for the characteristics of electrical noise by the level of AC input voltage. In order to further improve the electrical properties of the $BaTiO_3$ based composite, glass frit, MgO, $Y_2O_3$, $Mn_3O$, $V_2O_5$, $BaCO_3$, $SiO_2$, and $Al_2O_3$ were used as additives. The electrical properties of the composites were determined by various amounts of additives and optimum sintering temperature. As a result of the optimized composite, it was possible to obtain a density of $5.77g/cm^3$, a dielectric constant of 1994, and an insulation resistance of $2.91{\times}10^{12}{\Omega}$ at an additive content of 5wt% and a sintering temperature of $1250^{\circ}C$. After forming a $2.5{\mu}m$ green sheet using the doctor blade method, a total of 77 layers were laminated and sintered at $1180^{\circ}C$. A decoupling capacitor with a size of $0.6mm(W){\times}0.3mm(L){\times}0.3mm(T)$ (width, length and thickness, respectively) and a capacitance of 100 nF was embedded using a PCB process for the 10G RF Transceiver modules. In the range of AC input voltage 400mmV @ 500kHz to 2200mV @ 900kHz, the embedded 10G RF Transceiver modules evaluated that it has better electrical performance than the non-embedded modules.

• 한국초전도ㆍ저온공학회논문지
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• 제16권1호
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• pp.14-18
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• 2014

The mechanical, electrical and thermal characteristics of insulating materials may significantly affect the performance and reliability of electrical devices using superconductors. General method to provide insulating layer between coated conductors is wrapping coated conductor with Kapton tape. But uniform and compact wrapping without failure or delamination in whole coverage for long length conductor is not a simple task and need careful control. Coating of insulating layer directly on coated conductor is desirable for providing compact insulating layer rather than wrapping insulating layers around conductor. Ceramic added polymer has been widely used as an insulating material for electric machine because of its good electrical insulating properties as well as excellent heat resistance and fairy good mechanical properties. The insulating layer of coated conductor should have high breakdown voltage and possesses suitable mechanical strength and maintain adhesiveness at the cryogenic temperature where it is used and withstand stress from thermal cycling. The insulating and mechanical properties of polymer can be improved by adding functional filler. In this study, insulating layer has been made by adding ceramic particles such as $SiO_2$ to a polymer resin. The size, amount and morphology of added ceramic powder was controlled and their effect on dielectric property of the final composite was measured and discussed for optimum composite fabrication.

• 한국재료학회지
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• 제5권1호
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• pp.3-11
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• 1995

Titanium oxide$(TiO_{2})$ 박막을 금속 알콕사이드 물질인 $(Ti(OC_3H_7)_4$(titanium isopropoxide)를 이용하여 p-Si(100) 기판위에 상압 화학 기상 증착법으로 증착시켰다. $(TiO_{2})$ 박막의 증착기구는 단순경 계층 이론으로 잘 설명되었으며, 화학반응 지배 기구 영역에서 겉보기 활성화 에너지는 18.2kcal/mol이었다. 증착된 박막은 $250^{\circ}C$이상에서 anatase상의 결정질 박막이었으며, 고온에서 열처리를 했을 경우에 rutile상으로 전이하였다. 박막의 상전이에는 열처리 온도외에도 열처리 시간과 박막의 두께가 영향을 미쳤다. 정전용량-전압특성을 조사해 본 결과 전형적인 MOS 다이오드구조의 특성을 보였으며, 비유전율 상수는 약 80정도였다. 제조한 $(TiO_{2})$ 박막의 열처리 공정 후에는 정전용량이 감소하였으며, 첨가물을 사용한 박막은 열처리 전과 같았다. 이때 $V_{FB}$는 -0.5 ~ 1.5V였다. 전기전도 특성을 알아보기 위하여 전류-전압특성을 조사하였으며 증착된 박막의 전도기구는 hopping mechanism이었다. 전기적 특성을 개선하기 위해서 후열처리 방법과 박막 증착시 Nb, Sr을 첨가하였으며, 모두 누설전류의 감소와 정전파괴전압의 증가를 가져왔다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.161-161
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• 2009

Ion bombarded inorganic materials for LC alignment has been researched as it provides controllability in a nonstop process for producing high-resolution displays. Many optically transparent insulators such as $SiOx$ and a-C:H have been investigated as potential candidates for inorganic alignment materials. Even so, LC orientation on a new material with superior capacity is required to produce high-performance displays. Many inorganic materials with high permittivities can reduce the voltage losses due to the LC alignment layer that are a trade-off for its capacitance. The minimum voltage for device operation can be applied to the LC under low external voltage using these materials. This means that low power consumption for LCD applications can be achieved using a high-k alignment structure in which the LC can be driven effectively with a low threshold voltage. Among the many other potential high-k oxides, HfO2 is considered to be one of the most promising due to its remarkable properties of high dielectric constant, relatively low leakage current, large band gap (5.68 eV), and high transparency. Due to these characteristics, HfO2 can be used in LC alignment to increase the capacitance of the inorganic alignment layer for low-voltage driving of LCs.

• 한국재료학회지
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• 제32권6호
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• pp.293-300
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• 2022

This study investigated a graded-refractive-index (GRIN) coating pattern capable of improving the light extraction efficiency of GaN light-emitting diodes (LEDs). The planar LEDs had total internal reflection thanks to the large difference in refractive index between the LED semiconductor and the surrounding medium (air). The main goal of this paper was to reduce the trapped light inside the LED by controlling the refractive index using various compositions of (TiO₂)_x(SiO₂)_1-x in GRIN LEDs consisting of five dielectric layers. Several types of multilayer LEDs were simulated and it was determined the transmittance value of the LEDs with many layers was greater than the LEDs with less layers. Then, the specific ranges of incident angles of the individual layers which depend on the refractive index were evaluated. According to theoretical calculations, the light extraction efficiency (LEE) of the five-layer GRIN is 25.29 %, 28.54 % and 30.22 %, respectively. Consequently, the five-layer GRIN LEDs patterned enhancement outcome LEE over the reference planar LEDs. The results suggest the increased light extraction efficiency is related to the loss of Fresnel transmission and the release of the light mode trapped inside the LED chip by the graded-refractive-index.

• 한국표면공학회지
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• 제29권6호
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.264-264
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• 2016

최근에 charge trap flash (CTF) 기술은 절연막에 전하를 트랩과 디트랩 시킬 때 인접한 셀 간의 간섭현상을 최소화하여 오동작을 줄일 수 있으며 낸드 플래시 메모리 소자에 적용되고 있다. 낸드 플래시 메모리는 고집적화, 대용량화와 비휘발성 등의 장점으로 인해 핸드폰, USB, MP3와 컴퓨터 등에 이용되고 있다. 기존의 실리콘 기반의 플래시 메모리 소자는 좁은 밴드갭으로 인해 투명하지 않고 고온에서의 공정이 요구되는 문제점이 있다. 따라서, 이러한 문제점을 개선하기 위해 실리콘의 대체 물질로 산화물 반도체 기반의 플래시 메모리 소자들이 연구되고 있다. 산화물 반도체 기반의 플래시 메모리 소자는 넓은 밴드갭으로 인한 투명성을 가지고 있으며 저온에서 공정이 가능하여 투명하고 유연한 기판에 적용이 가능하다. 다양한 산화물 반도체 중에서 비정질 In-Ga-Zn-O (a-IGZO)는 비정질임에도 불구하고 우수한 전기적인 특성과 화학적 안정성을 갖기 때문에 많은 관심을 받고 있다. 플래시 메모리의 고집적화가 요구되면서 절연막에 high-k 물질을 atomic layer deposition (ALD) 방법으로 적용하고 있다. ALD 방법을 이용하면 우수한 계면 흡착력과 균일도를 가지는 박막을 정확한 두께로 형성할 수 있는 장점이 있다. 또한, high-k 물질을 절연막에 적용하면 높은 유전율로 인해 equivalent oxide thickness (EOT)를 줄일 수 있다. 특히, HfOx와 AlOx가 각각 trap layer와 blocking layer로 적용되면 program/erase 동작 속도를 증가시킬 수 있으며 넓은 밴드갭으로 인해 전하손실을 크게 줄일 수 있다. 따라서 본 연구에서는 ALD 방법으로 AlOx와 HfOx를 게이트 절연막으로 적용한 a-IGZO 기반의 thin-film transistor (TFT) 플래시 메모리 소자를 제작하여 메모리 특성을 평가하였다. 제작 방법으로는, p-Si 기판 위에 열성장을 통한 100 nm 두께의 SiO2를 형성한 뒤, 채널 형성을 위해 RF sputter를 이용하여 70 nm 두께의 a-IGZO를 증착하였다. 이후에 소스와 드레인 전극에는 150 nm 두께의 In-Sn-O (ITO)를 RF sputter를 이용하여 증착하였고, ALD 방법을 이용하여 tunnel layer에 AlOx 5 nm, trap layer에 HfOx 20 nm, blocking layer에 AlOx 30 nm를 증착하였다. 최종적으로, 상부 게이트 전극을 형성하기 위해 electron beam evaporator를 이용하여 platinum (Pt) 150 nm를 증착하였고, 계면 결함을 최소화하기 위해 퍼니스에서 질소 가스 분위기, $400^{\circ}C$, 30 분의 조건으로 열처리를 했다. 측정 결과, 103 번의 program/erase를 반복한 endurance와 104 초 동안의 retention 측정으로부터 큰 열화 없이 메모리 특성이 유지되는 것을 확인하였다. 결과적으로, high-k 물질과 산화물 반도체는 고성능과 고집적화가 요구되는 향후 플래시 메모리의 핵심적인 물질이 될 것으로 기대된다.