• 제목/요약/키워드: $SiO_2$ Buffer Layer

검색결과 165건 처리시간 0.043초

AIN 버퍼층을 사용한 MFIS 구조의 제작 및 특성 (Fabrications and properties of MFIS structure using AIN buffer layer)

  • 정순원;김용성;이남열;김진규;정상현;김광호;유병곤;이원재;유인규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.29-32
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    • 2000
  • Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO$_{3}$/AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$.cmcm

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$CaF_2$ 박막의 전기적, 구조적 특성 (Eelctrical and Structural Properties of $CaF_2$Films)

  • 김도영;최석원;이준신
    • 한국전기전자재료학회논문지
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    • 제11권12호
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    • pp.1122-1127
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    • 1998
  • Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

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혼성물리화학기상 증착법에 의한 알루미나 완충층을 가진 실리콘 기판 위의 $MgB_2$ 박막제조에 대한 연구 (Deposition of $MgB_2$ Thin Films on Alumina-Buffered Si Substrates by using Hybrid Physical-Chemical Vapor Deposition Method)

  • 이태경;박세원;성원경;허지영;정순길;이병국;안기석;강원남
    • Progress in Superconductivity
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    • 제9권2호
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    • pp.177-182
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    • 2008
  • [ $MgB_2$ ] thin films were fabricated using hybrid physical-chemical vapor deposition (HPCVD) method on silicon substrates with buffers of alumina grown by using atomic layer deposition method. The growth war in a range of temperatures $500\;{\sim}\;600^{\circ}C$ and under the reactor pressures of $25\;{\sim}\;50\;Torr$. There are some interfacial reactions in the as-grown films with impurities of mostly $Mg_2Si$, $MgAl_2O_4$, and other phases. The $T_c$'s of $MgB_2$ films were observed to be as high as 39 K, but the transition widths were increased with growth temperatures. The magnetization was measured as a function of temperature down to the temperature of 5 K, but the complete Meissner effect was not observed, which shows that the granular nature of weak links is prevailing. The formation of mostly $Mg_2Si$ impurity in HPCVD process is discussed, considering the diffusion and reaction of Mg vapor with silicon substrates.

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고밀도 플라즈마에 의한 $CeO_2$ 박막의 식각 메커니즘 연구 (A Study on the etching mechanism of $CeO_2$ thin film by high density plasma)

  • 오창석;김창일
    • 대한전자공학회논문지SD
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    • 제38권12호
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    • pp.8-13
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    • 2001
  • $CeO_2$ 박막은 강유전체 메모리 디바이스 응용을 위한 금속-강유전체-절연체-실리콘 전계효과 트랜지스터 구조에서의 강유전체 박막과 실리콘 기판 사이의 완충층으로서 제안되어지고 있다. 본 논문에서는 $CeO_2$ 박막을 유도 결합 플라즈마를 이용하여 $Cl_2$/Ar 가스 혼합비에 따라 식각하였다. 식각 특성을 알아보기 위한 실험조건으로는 RF 전력 600 W, dc 바이어스 전압 -200 V, 반응로 압력 15 mTorr로 고정하였고 $Cl_2$($Cl_2$+Ar) 가스 혼합비를 변화시키면서 실험하였다. $Cl_2$/($Cl_2$+Ar) 가스 혼합비가 0.2일때 $CeO_2$ 박막의 식각속도는 230 ${\AA}$/min으로 가장 높았으며 또한 $YMnO_3$에 대한 $CeO_2$의 선택비는 1.83이였다. 식각된 $CeO_2$ 박막의 표면반응은 XPS와 SIMS를 통해서 분석하였다. XPS 분석 결과 $CeO_2$ 박막의 표면에 Ce와 Cl의 화학적 반응에 의해 CeCl 결합이 존재함을 확인하였고, 또한 SIMS 분석 결과로 CeCl 결합을 확인하였다. $CeO_2$ 박막의 식각은 Cl 라디칼의 화학적 반응의 도움을 받으며 Ce 원자는 Cl과 반응을 하여 CeCl과 같은 혼합물로 $CeO_2$ 박막 표면에 존재하며 이들 CeCl 혼합물은 Ar 이온들의 충격에 의해 물리적으로 식각 되어진다.

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A Materials Approach to Resistive Switching Memory Oxides

  • Hasan, M.;Dong, R.;Lee, D.S.;Seong, D.J.;Choi, H.J.;Pyun, M.B.;Hwang, H.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제8권1호
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    • pp.66-79
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    • 2008
  • Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides ($Nb_2O_5$, and $ZrO_x$) and subsequently the resistive switching of $Cu_xO$ and heavily Cu-doped $MoO_x$ film for their compatibility with modem transistor-process cycles. Single-crystalline Nb-doped $SrTiO_3$ (NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.