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http://dx.doi.org/10.5762/KAIS.2016.17.5.305

A study on the improvement of work flow and productivity in complex manufacturing line by employing the effective process control methods  

Park, Kyungmin (School of Business, Kwangwoon University)
Jeong, Sukjae (School of Business, Kwangwoon University)
Publication Information
Journal of the Korea Academia-Industrial cooperation Society / v.17, no.5, 2016 , pp. 305-315 More about this Journal
Abstract
Due to the change from small volume production to small quantity batch production systems, individual companies have been attempting to produce a wide range of operating strategies, maximize their productivity, and minimize their WIP level by operating with the proper cycle time to defend their market share. In particular, using a complex workflow and process sequence in the manufacturing line has some drawbacks when it comes to designing the production strategy by applying analytical models, such as mathematical models and queueing theory. For this purpose, this paper uses three heuristic algorithms to solve the job release problem at the bottleneck workstation, product mix problem in multi-purpose machine(s), and batch size and sequence in batch machine(s). To verify the effectiveness of the proposed methods, a simulation analysis was performed. The experimental results demonstrated that the combined application of the proposed methods showed positive effects on the reduction of the cycle time and WIP level, and improvement of the throughput.
Keywords
Complex manufacturing Line; Job release; Product mix; batch size and Job sequence;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 S. W. Yoon, Y. J. Cho and S. J. Jeong, "Combination effects analysis of bottleneck-load order review/release and the dispatching rule: Application to a printed circuit board manufacturing line with multiple bottlenecks", International Journal of Precision Engineering and Manufacturing, Vol.15, No.8, pp.1725-1732, 2014. DOI: http://dx.doi.org/10.1007/s12541-014-0525-4   DOI
2 Chen C. F, Wu K. J, Chang C. T, Wong D. S. H and Jang S. S, "Generation and verification of optimal dispatching policies for multi-product multi-tool semiconductor manufacturing processes", Computers and Chemical Engineering, Vol.52, No.3, pp.112-121, 2013. DOI: http://dx.doi.org/10.1016/j.compchemeng.2012.12.009   DOI
3 Thiesse F and Fleisch E, "On the value of location information to lot scheduling in complex manufacturing processes", International Journal of Production Economics, Vol.112, No.2, pp.532-547, 2008. DOI: http://dx.doi.org/10.1016/j.ijpe.2007.05.006   DOI
4 Vinod V and Sridharan R, "Simulation modeling and analysis of due-date assignment methods and scheduling decision rules in a dynamic job shop production system", International Journal of Production Economics, Vol.129, No.1, pp.127-146, 2011. DOI: http://dx.doi.org/10.1016/j.ijpe.2010.08.017   DOI
5 Weigert G, Klemmt A and Horn S, "Design and validation of heuristic algorithms for simulation-based scheduling of a semiconductor Backend facility", International Journal of Production Research, Vol.47, No.8, pp.2165-2184, 2009. DOI: http://dx.doi.org/10.1080/00207540902744784   DOI
6 GRAVES, R. J., KONOPKA, J. M., & MILNE, R. J. (1995). Literature review of material flow control mechanisms. Production Planning & Control, 6(5), 395-403. DOI: http://dx.doi.org/10.1080/09537289508930296   DOI
7 Glassey, C.R. and Resende, M.C.G., "A Scheduling Rule for Job Release in Semiconductor Fabrication,", Operations Research Letters, 7, 213-217, 1998. DOI: http://dx.doi.org/10.1016/0167-6377(88)90033-8   DOI
8 Fu M, Askin R, Fowler J, Haghnevis M, Keng N, Pettinato J. S and Zhang M, "Batch production scheduling for semiconductor back-end operations", Semiconductor Manufacturing, IEEE Transactions, Vol.24, No.2, pp.249-260, 2011. DOI: http://dx.doi.org/10.1109/TSM.2011.2114900   DOI
9 Monch J. W, Fowler S, Dauzere-Peres S. J and Mason O. R, "A survey of problem, solution, and future challenges in scheduling semiconductor manufacturing operations", Journal of Scheduling, Vol.14, No.6, pp.583-599, 2011. DOI: http://dx.doi.org/10.1007/s10951-010-0222-9   DOI
10 Chen T. L, "A self-adaptive agent-based fuzzy-neural scheduling system for a wafer fabrication factory", Expert Systems with Applications, Vol.38, No.6, pp.7158-7168, 2011. DOI: http://dx.doi.org/10.1016/j.eswa.2010.12.044   DOI
11 Cheng H. C and Chiang T. C, "A two-stage hybrid memetic algorithm for multi objective job shop scheduling", Expert Systems with Applications, Vol.38, No.9, pp.10983-10998, 2011. DOI: http://dx.doi.org/10.1016/j.eswa.2011.02.142   DOI
12 Sha D. Y, Hsu S. Y, Che Z. H and Chen C. H, "A dispatching rule for photolithography scheduling with an on-line rework strategy", Computers and Industrial Engineering, Vol.50, No.3, pp.233-247, 2006. DOI: http://dx.doi.org/10.1016/j.cie.2006.04.002   DOI
13 Kayton D, Teyner T, Schwartz C and Uzsoy r, "Effects of dispatching and down time on the performance of wafer fabs operating under theory of constraints", Proceedings of the 1996 IEEE/CPMT international electronics manufacturing technology symposium 14-16 October Austin TX USA, pp.49-56, 1996. DOI: http://dx.doi.org/10.1109/IEMT.1996.559681   DOI
14 Uzsoy R, Church L. K and Ovacik I. M, "Dispatching rules for semiconductor testing operations: a computational study", Proceedings of the thirteenth IEEE/CHMT international electronics manufacturing technology symposium 28-30 September, pp.272-276, 1992. DOI: http://dx.doi.org/10.1109/IEMT.1992.639903   DOI
15 H. J. Yoon and J. G. Kim, "Heuristic scheduling policies for a semiconductor wafer fabrication facility: minimizing variation of cycle times", The International Journal of Advanced Manufacturing Technology, Vol.67, No.1, pp.171-180, 2013. DOI: http://dx.doi.org/10.1007/s00170-013-4762-y   DOI