1 |
Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, "A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link", IEEE Journal of Solid-State Circuits, vol.42, no.1, pp.111-121, Jan. 2007. DOI: http://dx.doi.org/10.1109/JSSC.2006.886554
DOI
ScienceOn
|
2 |
Kazutaka Kasuga, Mitsuko Saito, Tsutomu Takeya, Noriyuki Miura, Hiroki Ishikuro and Tadahiro Kuroda, "A Wafer Test Method of Inductive-Coupling Link" IEEE Asian Solid- State Circuits Conference, pp.301-304, Nov. 2009. DOI: http://dx.doi.org/10.1109/ASSCC.2009.5357251
DOI
|
3 |
Shin Jae-Young, Song Byung-Moo, "Fabrication and Characteristic of Multi-Layer Chip Inductor", The Korean Ceramic Society, Ceramist, vol.2, no.4, pp.11-17, 1999.
|
4 |
Lei Luo, John M. Wilson, Stephen E. Mick, JianXu, Liang Zhang, and Paul D. Franzon, "3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver", IEEE Journal of Solid-State Circuits, vol.41, no.1, pp.287-296, Jan. 2006. DOI: http://dx.doi.org/10.1109/JSSC.2005.859881
DOI
ScienceOn
|
5 |
Sanjay K. Thakur, Rubin A. Parekhji, A. N. Chandorkar, "On-chip Test and Repair of Memories for Static and Dynamic Faults", IEEE International test conference, 2006.
|
6 |
John Wilson, Member, Stephen Mick, Jian Xu, Member, Lei Luo, Salvatore Bonafede, Alan Huffman, "Fully Integrated AC Coupled Interconnect, Using Buried Bumps", IEEE Trans. Actionson Advanced Packing, vol.30, no.2, pp.191-199, May 2007. DOI: http://dx.doi.org/10.1109/TADVP.2007.896920
DOI
ScienceOn
|