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http://dx.doi.org/10.14372/IEMEK.2019.14.5.227

Design of CPS Architecture for Ultra Low Latency Control  

Kang, Sungjoo (ETRI)
Jeon, Jaeho (ETRI)
Lee, Junhee (ETRI)
Ha, Sujung (ETRI)
Chun, Ingeol (ETRI)
Publication Information
IEMEK Journal of Embedded Systems and Applications / v.14, no.5, 2019 , pp. 227-237 More about this Journal
Abstract
Ultra-low latency control is one of the characteristics of 5G cellular network services, which means that the control loop is handled in milliseconds. To achieve this, it is necessary to identify time delay factors that occur in all components related to CPS control loop, including new 5G cellular network elements such as MEC, and to optimize CPS control loop in real time. In this paper, a novel CPS architecture for ultra-low latency control of CPS is designed. We first define the ultra-low latency characteristics of CPS and the CPS concept model, and then propose the design of the control loop performance monitor (CLPM) to manage the timing information of CPS control loop. Finally, a case study of MEC-based implementation of ultra-low latency CPS reviews the feasibility of future applications.
Keywords
Ultra low latency control; Cyber-Physical systems; Multi-access edge computing; 5G cellular network; CPS control loop;
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