| 1 |
P. K. Dubey, G. B. Adams III, and M. J. Flynn, "Instruction Window Size Trade-Offs and Characterization of Program Parallelism," IEEE Transactions on Computers, Vol. 43, pp. 431-442, 1994.
DOI
ScienceOn
|
| 2 |
T. Yeh, D. T. Marr, and Y. N. Patt, "Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache," The 7th International Conference on Supercomputing, pp. 67-76, 1993.
|
| 3 |
이종복, "대형 윈도우에서 다중 분기 예측법을 이용하는 수퍼스칼라 프로세서의 프로화일링 성능 모델," 대한전기학회논문지, 제58권, 제7 호, pp. 1443-1449, 2009. 7.
과학기술학회마을
|
| 4 |
T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, pp. 320-348, 2002.
DOI
ScienceOn
|
| 5 |
박상수, "다중 멀티미디어 스트리밍을 위한 멀티코어 시스템 기반의 실시간 스케줄링 기법," 한국멀티미디어학회논문지, 제14권, 제11호, pp. 1478-1490. 2011년 11월.
과학기술학회마을
DOI
ScienceOn
|
| 6 |
T. N. Vijaykumar and G. S. Sohi, "Task Selection for a Multiscalar Processor," 31st International Symposium on Microarchitecture, Dec. pp. 81-92, 1998.
|
| 7 |
T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," Proceedings of the 19th International Symposium on Computer Architecture, pp. 124-134, 1992.
|
| 8 |
A. Rico, A. Duran. F. Cabarcas, Y. Etsion, A. Ramirex, and M. Valero, "Trace-Driven Simulation of Multithreaded Applications," ISPASS, pp. 87-96, Apr. 2011.
|
| 9 |
T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, Vol. 35, No. 2, pp. 59-67, 2002.
DOI
ScienceOn
|
| 10 |
S. Biswas, D. Franklin, A. Savage, R. Dixon, T. Sherwood, and F. T. Chong, "Multi-Execution : Multicore Caching for Data-Similar Executions," Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 164-173, 2009.
|
| 11 |
M. Monchiero, J. H. Ahn, A. Falcon, D. Ortega, and P. Faraboschi, "How to Simulate 1000 Cores," ACM SIGARCH Computer Architecture News Archive, Vol. 37, Issue 2, pp. 10-19, 2009.
DOI
|
webmaster
