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Design and Fabrication of a Ku-Band Planar Limiter with PIN Diodes  

Kim Tak-Young (SK Telecom Central Region Network Division)
Yang Seong-Sik (Department of Radio and Science Engineering, Chungnam National University)
Yeom Kyung-Whan (Department of Radio and Science Engineering, Chungnam National University)
Kong Deok-Kyu (Agency for Defense Development)
Kim So-Su (Agency for Defense Development)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.17, no.4, 2006 , pp. 368-379 More about this Journal
Abstract
In this paper, the analytic design technique for a planar PIN diode limiter is presented rather than the conventional design heavily relying on the experiments. The novel analysis fur the PIN diode limiter shows the leakage is composed of two kinds of leakages and the relationship between the leakages and the PIN diode parameters. The designed limiter consists of 3 stages; the front two stages with two PM diodes and the final stage with Schottky diode pair. The fabricated limiter shows the insertion loss of 0.8 dB for the small input power, spike leakage of 12 Bm, flat leakage of 12 dBm for the 20 W RF power.
Keywords
PIN Diode; Limiter; Spike Leakage; Flat Leakage;
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