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http://dx.doi.org/10.7471/ikeee.2022.26.4.714

A 166MHz Phase-locked Loop-based Frequency Synthesizer  

Minjun, Cho (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Changmin, Song (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Young-Chan, Jang (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.26, no.4, 2022 , pp. 714-721 More about this Journal
Abstract
A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.
Keywords
phase-locked loop; frequency synthesizer; frequency divider; multi-phase clock; SoC;
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