[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.7471/ikeee.2022.26.4.659

Chip Implementation of 830-Mb/s/pin Transceiver for LPDDR2 Memory Controller

Jong-Hyeok, Lee (Dept. of Electronics Engineering, Graduate School, Kumoh National Institute of Technology)
Chang-Min, Song (Dept. of Electronics Engineering, Graduate School, Kumoh National Institute of Technology)
Young-Chan, Jang (Dept. of Electronics Engineering, Graduate School, Kumoh National Institute of Technology)

Publication Information

Journal of IKEEE / v.26, no.4, 2022 , pp. 659-670 More about this Journal

Abstract

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

Keywords

LPDDR2; Memory interface; SerDes; Read time calibration; ZQ calibration;

Citations & Related Records

Reference

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KSCI

Chip Implementation of 830-Mb/s/pin Transceiver for LPDDR2 Memory Controller LPDDR2 메모리 컨트롤러를 위한 830-Mb/s/pin 송수신기 칩 구현

Chip Implementation of 830-Mb/s/pin Transceiver for LPDDR2 Memory Controller