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http://dx.doi.org/10.7471/ikeee.2022.26.4.577

Introduction to System Modeling and Verification of Digital Phase-Locked Loop  

Shinwoong, Kim (School of Computer Science and Electrical Engineering, Handong Global University)
Publication Information
Journal of IKEEE / v.26, no.4, 2022 , pp. 577-583 More about this Journal
Abstract
Verilog-HDL-based modeling can be performed to confirm the fast operation characteristics after setting the design parameters of each block considering the stability of the system by performing linear phase-domain modeling on the phase-locked loop. This paper proposed Verilog-HDL modeling including DCO noise and DTC nonlinear characteristic. After completing the modeling, the time-domain transient simulation can be performed to check the feasibility and the functionality of the proposed PLL system, then the phase noise result from the system design based on the functional model can be verified comparing with the ideal phase noise graph. As a result of the comparison of simulation time (6 us), the Verilog-HDL-based modeling method (1.43 second) showed 484 times faster than the analog transistor level design (692 second) implemented by TSMC 0.18-㎛.
Keywords
Phase-locked loop; Digital PLL; PLL modeling; Verilog-HDL modeling; DTC; TDC;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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