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http://dx.doi.org/10.7471/ikeee.2022.26.3.333

Determination of optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS device for ESD protection  

Seo, Yong-Jin (Dept. of Fire Service, Sehan University)
Publication Information
Journal of IKEEE / v.26, no.3, 2022 , pp. 333-340 More about this Journal
Abstract
Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N- drift and N+ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.
Keywords
ESD (electrostatic discharge); DDDNMOS (double diffused drain N-type MOSFET); double snapback; Vav(avalanche breakdown voltage); design window; simulation. DPS(double polarity source); colligation;
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