1 |
S. Oleg, S. Hossein, S. Manoj, "ESD Protection Device and Circuit Design for Advanced CMOS Technologies," Springer, 2008.
|
2 |
Albert Z. H. Wang, On-Chip ESD Protection for Integrated Circuits 2nd ed, Springer, 2002
|
3 |
M. D. Ker and C. C. Yen, "Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latch up-Like Failure During System-Level ESD Test," IEEE J.Solid-State Circuits, vol.43, no.11, pp.2533-2545. 2008. DOI: 10.1109/JSSC.2008.2005451
DOI
|
4 |
A. V. Vladislav, S. Andrei, "ESD Design for Analog Circuits," Springer, 2010
|
5 |
M.-D. Ker and S.-H. Chen, "Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology," IEEE J. Solid-State Circuits, vol.42, no.5, pp.1158-1168, 2007. DOI: 10.1109/JSSC.2007.894823
DOI
|
6 |
M.-D. Ker and K.-C. Hsu, "Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits," IEEE Trans. Device Mater. Rel., vol.5, no.2, pp. 235-249, 2005. DOI: 10.1109/TDMR.2005.846824
DOI
|
7 |
F. Du et al., "An improved silicon-controlled rectifier (SCR) for lowvoltage ESD application," IEEE Trans. Electron Devices, vol.67, no.2, pp. 576-581, 2020. DOI: 10.1109/TED.2019.2961124
DOI
|