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http://dx.doi.org/10.7471/ikeee.2021.25.4.778

The Verification of Channel Potential using SPICE in 3D NAND Flash Memory  

Kim, Hyunju (Dept. of Electronics Engineering, Korea National University of Transportation)
Kang, Myounggon (Dept. of Electronics Engineering, Korea National University of Transportation)
Publication Information
Journal of IKEEE / v.25, no.4, 2021 , pp. 778-781 More about this Journal
Abstract
In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(SilvacoTM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.
Keywords
3D NAND Flash memory; Down Coupling Phenomenon(DCP); Natural Local Self; Boosting(NLSB); SPICE; Technology Computer Aided Design(TCAD);
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1 Y. Kim, J. G. Yun, S. H. Park, W. Kim, J. Y. Seo, M. Kang, K. C. Ryoo, J. H. Oh, J. H. Lee, H. Shin, and B. G. Park, "Three-dimensional NAND Flash architecture design based on single-crystalline stacked array," IEEE Trans. Electron Devices, vol.59, no.1, pp.35-45, 2012. DOI: 10.1109/TED.2011.2170841   DOI
2 Y. Kim, M. Kang, S. H. Park, and B. G. Park, "Three-dimensional NAND Flash memory based on single-crystalline channel stacked array," IEEE Electron Device Letters, vol.34, no.8, pp.990-992, 2013. DOI: 10.1109/LED.2013.2262174   DOI
3 M. K. Jeong, S. M. Joe, B. S. Jo, H. J. Kang, J. H. Bae, K. R. Han, E. Choi, G. Cho, S. K. Park, B. G. Park, and J. H. Lee, "Characterization of traps in 3-D stacked NAND Flash memory devices with tube-type poly-Si channel structure," IEEE International Electron Devices Meeting, pp.9.3.1-9.3.4, 2012. DOI: 10.1109/IEDM.2012.6479010   DOI
4 M. Kang, I. H. Park, I. J. Chang, K. Lee, S. Seo, B. G. Park, and H. Shin, "An accurate compact model considering direct-channel interference of adjacent cells in sub-30-nm NAND Flash technologies," IEEE Electron Device Letters, vol.33, no.8, pp. 1114-1116, 2012. DOI: 10.1109/LED.2012.2201442   DOI
5 Silvaco, Inc., "Atlas User's Manual, Silvaco V ersion. 5.19.20.", http://www.silvaco.com/products/tcad/device_simulation/atlas/atlas.html
6 M. Park, K. Kim, J. H. Park, and J. H. Choi, "Direct field effect of neighboring cell transistor on cell-to-cell interference of NAND Flash cell arrays," IEEE Electron Device Letters, vol.30, no.2, pp.174-177, 2008. DOI: 10.1109/LED.2008.2009555   DOI
7 Y. Kim and M. Kang, "Down-coupling phenomenon of floating channel in 3D NAND Flash memory" IEEE Electron Device Letters, vol.37, no.12, pp. 1566-1569, 2016. DOI: 10.1109/LED.2016.2619903   DOI
8 M. Kang and Y. Kim, "Natural local self-boosting effect in 3D NAND Flash memory," IEEE Electron Device Letters, vol.38, pp.1236-1239, 2017. DOI: 10.1109/LED.2017.2736541   DOI