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http://dx.doi.org/10.7471/ikeee.2021.25.4.634

FPGA-Based Acceleration of Range Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging  

Jeong, Dongmin (Department of Smart Air Mobility, Korea Aerospace University)
Lee, Wookyung (School of Electronics and Information Engineering, Korea Aerospace University)
Jung, Yunho (Department of Smart Air Mobility, Korea Aerospace University)
Publication Information
Journal of IKEEE / v.25, no.4, 2021 , pp. 634-643 More about this Journal
Abstract
In this paper, an FPGA-based acceleration scheme of range Doppler algorithm (RDA) is proposed for the real time synthetic aperture radar (SAR) imaging. Hardware architectures of matched filter based on systolic array architecture and a high speed sinc interpolator to compensate range cell migration (RCM) are presented. In addition, the proposed hardware was implemented and accelerated on Xilinx Alveo FPGA. Experimental results for 4096×4096-size SAR imaging showed that FPGA-based implementation achieves 2 times acceleration compared to GPU-based design. It was also confirmed the proposed design can be implemented with 60,247 CLB LUTs, 103,728 CLB registers, 20 block RAM tiles and 592 DPSs at the operating frequency of 312 MHz.
Keywords
FFT; FPGA; radar; RDA; SAR; signal processing; systolic array;
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