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http://dx.doi.org/10.7471/ikeee.2021.25.4.625

A Scalable Montgomery Modular Multiplier  

Choi, Jun-Baek (Ranix Inc.)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.25, no.4, 2021 , pp. 625-633 More about this Journal
Abstract
This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, NPE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for NPE=1 and NPE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for NPE=1 and 3.5 million times/sec for NPE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).
Keywords
Modular multiplication; Montgomery multiplication; ECC; scalable architecture; scalable multiplier;
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1 M. Shieh and W. Lin, "Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures," in IEEE Transactions on Computers, vol.59, no.8, pp.1145-1151, 2010. DOI: 10.1109/TC.2010.72   DOI
2 N. Koblitz, "Elliptic curve cryptosystems," Mathematics of Computation, vol.48, no.177, pp.203-209, 1987.   DOI
3 S. Sugiyama, H. Awano and M. Ikeda, "Low Latency 256-bit Fp ECDSA Signature Generation Crypto Processor," IEICE Transaction on Fundamentals, vol.E101-A, no.12, pp.2290-2296, 2018. DOI: 10.1587/transfun.E101.A.2290   DOI
4 M. Knezevic, V. Nikov, and P. Rombouts, "Low-latency ECDSA signature verification-A road toward safer traffic," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol.24, no.11, pp.3257-3267, 2016. DOI: 10.1109/TVLSI.2016.2557965   DOI
5 D. S. Kim and K. Y. Shin, "Montgomery Multiplier supporting Dual-Field Modular Multiplication," Journal of the Korea Institute of Information and Communication Engineering, vol.24, no.6, pp.736-743, 2020. DOI: 10.6109/jkiice.2020.24.6.736   DOI
6 M. Amine, E. M. Nadia, L. Ronan, J. B. Rigaud, B. Belgacem, M. Sihem and M. Mohsen, "A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs," Journal of Hardware and Systems Security, vol.1, issue3, pp.219-236, 2017. DOI: 10.1007/s41635-017-0018-x.   DOI
7 S. Kuang, C. Liang and C. Chen, "An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol.63, no.6, pp.568-572, 2016. DOI: 10.1109/TCSII.2016.2530801   DOI
8 Certicom, Standards for Efficient Cryptography, SEC 2: Recommended Elliptic Curve Domain Parameters, Version 1.0, 2000.
9 P. L. Montgomery, "Modular multiplication without trial division," Math. of Computation, vol.44, no.170, pp.519-521, 1985.   DOI
10 A. F. Tenca and C. K. Koc, "A Scalable Architecture for Montgomery Multiplication," International Workshop on Cryptographic Hardware and Embedded Systems, Springer, Heidelberg, vol.1717, pp.94-108, 1999.   DOI
11 ITS Committee, "IEEE standard for wireless access in vehicular environments-security services for applications and management messages," IEEE Vehicular Technology Society, Vol.1609, No.2, 2013. DOI: 10.1109/IEEESTD.2016.7426684   DOI
12 M. Selim Hossain and Y. Kong, "FPGA-based efficient modular multiplication for Elliptic Curve Cryptography," 2015 International Telecommunication Networks and Applications Conference (ITNAC), Sydney, NSW, pp.191-195, 2015, DOI: 10.1109/ATNAC.2015.7366811.   DOI
13 B. Zhang, Z. Cheng and M. Pedram, "High-Radix Design of a Scalable Montgomery Modular Multiplier with Low Latency," IEEE Transactions on Computers, Accepted for publication, 2021. DOI: 10.1109/TC.2021.3052999.   DOI
14 K. Javeed, X. Wang and M. Scott, "Serial and parallel interleaved modular multipliers on FPGA platform," 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, pp.1-4, 2015. DOI: 10.1109/FPL.2015.7293986.   DOI
15 K. Safiullah, J. Khalid and S. Y. Ali, "High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications," Microprocessor and Microsystems, vol.62, pp.91-101, 2018. DOI: 10.1016/j.micpro.2018.07.005.   DOI
16 J. B. Choi, "A Scalable ECC Processor Supporting Prime Field Elliptic Curves," Master Thesis, Kumoh National Institute of Technology, 2021.