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http://dx.doi.org/10.7471/ikeee.2021.25.3.473

A Study on the Circuit Design Method of CNTFET SRAM Considering Carbon Nanotube Density  

Cho, Geunho (Department of Electronic Engineering, Seokyeong University)
Publication Information
Journal of IKEEE / v.25, no.3, 2021 , pp. 473-478 More about this Journal
Abstract
Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.
Keywords
SRAM; CNTFET; CNT; CNT Density; Digital Circuit;
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