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http://dx.doi.org/10.7471/ikeee.2021.25.2.376

A Study on ESD Protection Circuit with Bidirectional Structure with Latch-up Immunity due to High Holding Voltage  

Jung, Jang-Han (Dept. of Electronics Engineering, Dankook University)
Do, Kyung-Il (Dept. of Electronics Engineering, Dankook University)
Jin, Seung-Hoo (Dept. of Electronics Engineering, Dankook University)
Go, Kyung-Jin (Dept. of Electronics Engineering, Dankook University)
Koo, Yong-Seo (Dept. of Electronics Engineering, Dankook University)
Publication Information
Journal of IKEEE / v.25, no.2, 2021 , pp. 376-380 More about this Journal
Abstract
In this paper, we propose a novel ESD protection device with Latch-up immunity properties due to high holding voltages by improving the structure of a typical SCR. To verify the characteristics of the proposed ESD circuit, simulations were conducted using Synopsys TCAD and presented compared to existing ESD protection circuits. Furthermore, the variation of electrical properties was verified using the design variable D1. Simulation results confirm that the proposed ESD protective circuit has higher holding voltage properties and bidirectional discharge properties compared to conventional ESD protective circuits. We validate the electrical properties with post-design TLP measurements using Samsung's 0.13um BCD process. And we verify that the proposed ESD protection circuit in this paper is well suited for high voltage applications in that it has a latch-up immunity due to improved holding voltage through optimization of design variables.
Keywords
ESD; Latch-up; SCR; Holding Voltage; DDSCR;
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1 K. D Kim "A Study on the Novel SCR Nano ESD Protection Device Design and Fabrication," j.inst.Korean.electr.electron.eng, vol.9, no.2, pp.83-91, 2005. DOI: 10.7471/ikeee.2017.21.3.234   DOI
2 R. G. Wagner, J. Soden and C. F. Hawkins, "Extend and Cost of EOS/ESD Damage in an IC Manufacturing Process," in Proc. of the 15th EOS/ESD Symp., pp.49-55, 1993. DOI: 10.7471/ikeee.2016.20.3.295   DOI
3 R. G. Wagner, J. Soden and C. F. Hawkins, "Extend and Cost of EOS/ ESD Damage in an IC Manufacturing Process," in Proc. of the 15th EOS/ESD Symp., pp.49-55, 1993. DOI: 10.7471/ikeee.2015.19.2.265   DOI
4 O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," in Proc. EOS/ESD Symp., pp.77-86. 2006.
5 Albert Z. H. Wang, "On-Chip ESD Protection for Integrated Circuits 2nd ed," Springer, 2002.
6 M. D. Ker and C. C. Yen, "Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latch up-Like Failure During System-Level ESD Test," IEEE J.Solid-State Circuits, vol.43, no.11, pp.2533-2545. 2008. DOI: 10.1109/JSSC.2008.2005451   DOI