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http://dx.doi.org/10.7471/ikeee.2021.25.2.302

12-bit 10-MS/s CMOS Pipeline Analog-to-Digital Converter  

Cho, Se-Hyeon (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Jung, Ho-yong (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Do, Won-Kyu (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Lee, Han-Yeol (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Jang, Young-Chan (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.25, no.2, 2021 , pp. 302-308 More about this Journal
Abstract
A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-Vpp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.
Keywords
Pipelined analog-to-digital converter; gain boosting; sample and hold amplifier; flash ADC; digital error corrector;
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