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http://dx.doi.org/10.7471/ikeee.2020.24.2.619

Low Resistance 3.3kV 4H-SiC Trench Shielded DMOSFET  

Cha, Kyu-hyun (Dept. of Electronics Engineering, Sogang University)
Kim, Kwang-su (Dept. of Electronics Engineering, Sogang University)
Publication Information
Journal of IKEEE / v.24, no.2, 2020 , pp. 619-625 More about this Journal
Abstract
In this paper, we propose a TS-DMOSFET(Trench Shielded DMOSFET) structure in which P+ shielding region is formed in a deeper region than C-DMOSFET(Conventional DMOSFET) and S-DMOSFET(Shielded DMOSFET). Using TCAD simulation to compare the static characteristics of TS-DMOSFET with C- and S-DMOSFET. As for the structure proposed, the doping is followed by the source trench process. Despite the fact that it is a SiC material, this allows it to form a P+ shielding region in a deep area. Followed by completely suppressing the reach-through effect. As a result, when the breakdown voltage of the three structures is 3.3kV, the Ron of TS-DMOSFET is 9.7mΩ㎠. Thus, it is 68% and 54% smaller than the Ron of C-DMOSFET and S-DMOSFET respectively.
Keywords
4H-SiC; Planar MOSFET; Trench; breakdown; on-resistance;
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