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http://dx.doi.org/10.7471/ikeee.2020.24.1.19

Three-phase 3-level and 2-level SVPWM Implementation with 100 kHz Switching Frequency using FPGA  

Moon, Kyeong-Rok (School of Electronic and Electrical Engineering, Hongik University)
Lee, Dong-Myung (School of Electronic and Electrical Engineering, Hongik University)
Publication Information
Journal of IKEEE / v.24, no.1, 2020 , pp. 19-24 More about this Journal
Abstract
This paper presents a 3-level, 2-level SVPWM technique with 100 kHz switching using Verilog HDL, one of the languages of FPGA. In the case of IGBT devices mainly used in inverters, they have a switching frequency around 20kHz. Recent research and development of next-generation power semiconductor devices such as GAN has enabled switching of more than 100kHz, which can miniaturize power converters, and apply various new algorithms due to the injection of harmonics. In the existing system using the IGBT, the control using the DSP is common, but the controller configuration for 100 kHz switching requires the use of FPGA. Therefore, this paper explains the theory and implementation of SVPWM applied to two-level and three-level inverters using FPGAs and verifies the performance through the output waveform. In addition, this paper implements 3-level SVPWM by using only one carrier instead of using two carriers in the conventional method.
Keywords
FPGA; SVPWM; 2-level; 3-level power converter; High switching frequency; Verilog HDL;
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