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http://dx.doi.org/10.7471/ikeee.2020.24.1.186

Multi-threaded system to support reconfigurable hardware accelerators on Zynq SoC  

Shin, Hyeon-Jun (Chips&Media)
Lee, Joo-Heung (Dept. of Electronic and Electrical Engineering, Hongik University)
Publication Information
Journal of IKEEE / v.24, no.1, 2020 , pp. 186-193 More about this Journal
Abstract
In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.
Keywords
HW/SW co-design; Reconfigurable hardware accelerator; Multi-threaded system; Image processing; JPEG;
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