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http://dx.doi.org/10.7471/ikeee.2020.24.1.161

Design of a Large-density MTP IP  

Kim, YoungHee (Dept. of Electronic Engineering, Changwon National University)
Ha, Yoon-Kyu (Dept. of Electronic Engineering, Changwon National University)
Jin, Hongzhou (Dept. of Electronic Engineering, Changwon National University)
Kim, SuJin (Magnachip Semiconductor)
Kim, SeungGuk (Magnachip Semiconductor)
Jung, InChul (Magnachip Semiconductor)
Ha, PanBong (Dept. of Electronic Engineering, Changwon National University)
Park, Seungyeop (Dept. of Electronic Engineering, Changwon National University)
Publication Information
Journal of IKEEE / v.24, no.1, 2020 , pp. 161-169 More about this Journal
Abstract
In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the VTP(Program Threshold Voltage) and the VTE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and VT and erase VT, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.
Keywords
MTP; IP; Hot Carrier Injection; BTBT; BCD Process;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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