Design of a Large-density MTP IP
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Kim, YoungHee
(Dept. of Electronic Engineering, Changwon National University)
Ha, Yoon-Kyu (Dept. of Electronic Engineering, Changwon National University) Jin, Hongzhou (Dept. of Electronic Engineering, Changwon National University) Kim, SuJin (Magnachip Semiconductor) Kim, SeungGuk (Magnachip Semiconductor) Jung, InChul (Magnachip Semiconductor) Ha, PanBong (Dept. of Electronic Engineering, Changwon National University) Park, Seungyeop (Dept. of Electronic Engineering, Changwon National University) |
1 | Y. Xu et al., "Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.63, No.11, pp.1064-1068, 2016. DOI: 10.1109/TCSII.2016.2548238 DOI |
2 | R. Strenz, "Embedded Flash Technologies and their Applications: Status & Outlook," Proceedings of IEEE IEDM, pp.9.4.1-9.4.4, 2011. DOI: 10.1109/IEDM.2011.6131521 |
3 | B. Wang et al., "Opportunities and Challenges in Multi-times-programmable Floating-Gate Logic Non-Volatile Memories," pp.22-25, 2008. DOI: 10.1109/NVSMW.2008.12 |
4 | F. Xu et al., "Key Design Techniques of A 40ns 16K Bits Embedded EEPROM Memory," 2004 International Conference on Communications, Circuits and Systems, Vol.2, pp.1516-1520, 2004. DOI: 10.1109/ICCCAS.2004.1346462 |
5 | A. Conte et al., "A High-Performance Very Low-Voltage Current Sense Amplifier for Nonvolatile Memory," IEEE J. Solid-State Circuits, Vol.40, No.2, pp.507-514, 2005. DOI: 10.1109/JSSC.2004.840985 DOI |
6 | G. S. Cho et al., "Design of a Small-Area, Low-Power, and High-Speed 128-KBit EEPROM IP for Touch-Screen Controllers," Journal of the Korean Institute of Maritime Information and Communication Sciences, Vol.13, No.12, pp.2633-2640, 2009. |
7 | Y. H. Kim et al., "Design of a Fast 256Kb EEPROM for MCU," JKIICE, Vol.19, No.3, pp. 567-574, 2015. DOI: 10.6109/jkiice.2015.19.3.567 |
8 | Heon Park et al., "Design of a Cell Verification Module for Large-Density EEPROMs," JKIIECT, Vol.10, No.2, pp.176-183, 2017. DOI: 10.17661/jkiiect.2017.10.2.176 |
9 | Y. H. Kim et al., "Design of 40ns 512Kb EEPROM IP," Proceedings of the 4th ICIECT 2018, pp.245-246, 2018. DOI: 10.17661/jkiiect.2017.10.5.455 |
10 | Y. H. Kim et al., "Design of MTP memory IP using vertical PIP capacitor," JKIIECT, 2020. |
11 | Y. K. Kim et al., "Design of Multi-time Programmable Memory for PMICs," ETRI journal, Vol.37, No.6, pp.1188-1198, 2015. DOI: 10.4218/etrij.15.0114.1428 DOI |
12 | H. Park et al., "Design of 512bit MTP IP for PMICs," Proceedings of AWAD conference, 2017. |
13 | Y. H. Kim, "Non-Volatile Memory Design," GSINTERVISION, 2016. |
14 | Y. H. Kim et al., "A Study on Memory Circuit Architecture," ETRI Research Report, 2017. |
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