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http://dx.doi.org/10.7471/ikeee.2019.23.4.1257

A 3-GSymbol/s/lane MIPI C-PHY Transceiver with Channel Mismatch Correction Circuit  

Choi, Seokwon (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Song, Changmin (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Jang, Young-Chan (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.23, no.4, 2019 , pp. 1257-1264 More about this Journal
Abstract
A 3-GSymbol/s/lane transceiver, which supports the mobile industry processor interface (MIPI) C-physical layer (PHY) specification version 1.1, is proposed. It performs channel mismatch correction to improve the signal integrity that is deteriorated by using three-level signals over three channels. The proposed channel mismatch correction is performed by detecting channel mismatches in the receiver and adjusting the delay times of the transmission data in the transmitter according to the detection result. The channel mismatch detection in the receiver is performed by comparing the phases of the received signals with respect to the pre-determined data pattern transmitted from the transmitter. The proposed MIPI C-PHY receiver is designed using a 65 nm complementary metal-oxide-semiconductor (CMOS) process with 1.2 V supply voltage. The area and power consumption of each transceiver lane are 0.136 ㎟ and 17.4 mW/GSymbol/s, respectively. The proposed channel mismatch correction reduces the time jitter of 88.6 ps caused by the channel mismatch to 34.9 ps.
Keywords
MIPI C-PHY; transceiver; channel mismatch correction; transmitter; receiver; phase detector;
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