Browse > Article
http://dx.doi.org/10.7471/ikeee.2019.23.4.1203

A software-controlled bandwidth allocation scheme for multiple router on-chip-networks  

Bui, Phan-Duy (Dept. of Information Technology and Telecommunication Engineering, Soongsil University)
Lee, Chanho (Dept. of Information Technology and Telecommunication Engineering, Soongsil University)
Publication Information
Journal of IKEEE / v.23, no.4, 2019 , pp. 1203-1207 More about this Journal
Abstract
As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.
Keywords
on-chip-network; SoC; bandwidth allocation; QoS; arbitration; multiple routers;
Citations & Related Records
연도 인용수 순위
  • Reference
1 S. Lee, C. Lee, and H.-J. Lee, "High Performance SoC On-chip-bus Architecture with Multiple Channels and Simultaneous Routing," Journal of IEEK, 44SD(4), pp. 322-329, 2007.
2 C.-M. Chung, D.-A. Chiang, and Y. Qing, "A comparative analysis of different arbitration protocols for multiple-bus multiprocessors," J. Computer Science Technology, vol.11, no.3, pp. 313-325, 1996. DOI: 10.1007/BF02943137   DOI
3 K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "The LOTTERYBUS on-chip communication architecture," IEEE Trans. Very Large Scale Integration (VLSI) System, vol.14, no.6, pp.596-608, 2006. DOI: 10.1109/TVLSI.2006.878210   DOI
4 ARM, "AMBA AXI Specification," Revision 2.0, 2010.
5 C. Lee, "On-chip-network Protocol for Efficient Network Utilization," Journal of IEEK, 47SD(1), pp.86-93, 2010.