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http://dx.doi.org/10.7471/ikeee.2019.23.3.925

SoC Implementation of Deblocking Filter for Block-based Compressed Images and Videos  

Seo, Gwang-Seok (Satrec Initiative)
Lee, Joo-Heung (Dept. of Electronic and Electrical Engineering, Hongik University)
Publication Information
Journal of IKEEE / v.23, no.3, 2019 , pp. 925-933 More about this Journal
Abstract
In this paper, we implement ZYNQ SoC-based post-processing system that utilizes partial reconfiguration to remove blocking artifacts generated by compression algorithm. Hardware implementation of the deblocking filter in a Field Programmable Gate Array (FPGA) provides high computational capability and can be partially reconfigured to process 1080p images in real time. Partially reconfigurable areas in FPGA can be utilized to use hardware more efficiently in highly resource-constrained embedded systems. Experimental results of the proposed system show improvement of visual quality both objectively and subjectively with 0.6dB higher PSNR after deblocking filtering process. The measured power consumption of the deblocking filter during run-time is 68.33mW.
Keywords
FPGA; Deblocking Filter; Zynq SoC; Partial Reconfiguration; High Level Synthesis;
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