1 |
Ahn, Jeong-Keun et al., (2018). Pair-wise staggering transmitter for single-ended parallel signaling. IEICE ELEX. 15. DOI: 10.1587/elex.15.20171238.
DOI
|
2 |
H. Jung et al., "A slew-rate controlled transmitter to compensate for the crosstalk- induced jitter of coupled microstrip lines," IEEE CICC 2010, San Jose, CA, pp.1-4, 2010. DOI: 10.1109/CICC.2010.5617597
|
3 |
H. Jung et al., "A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines," in IEEE JSSC, vol.47, no.9, pp.2068-2079, 2012. DOI: 10.1109/JSSC.2012.2197233
DOI
|
4 |
S. Kao et al., "A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection," in IEEE JSSC, vol.48, no.2, pp.391-404, 2013. DOI: 10.1109/JSSC.2012.2227604
DOI
|
5 |
S. Yuan et al., "A -Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS," 2015 IEEE CICC, pp.1-4, 2015. DOI: 10.1109/CICC.2015.7338414
DOI
|
6 |
C. Aprile et al., "An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels," in IEEE JSSC, vol.53, no.3, pp.861-872, 2018. DOI: 10.1109/JSSC.2017.2783679
|
7 |
T. Oh et al., "A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os," in IEEE JSSC, vol.46, no.8, pp.1843-1856, 2011. DOI: 10.1109/JSSC.2011.2151410
DOI
|
8 |
S. Kao et al., "A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection," in IEEE JSSC, vol.48, no.11, pp.2815-2826, 2013. DOI: 10.1109/JSSC.2013.2282116
DOI
|
9 |
H. Jung et al., "A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control," in IEEE JSSC, vol.44, no.11, pp.2891-2900, 2009. DOI: 10.1109/JSSC.2009.2028917
DOI
|
10 |
S. Lee et al., "A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation," in IEEE JSSC, vol.48, no.9, pp. 2118-2127, 2013. DOI: 10.1109/JSSC.2013.2264618
DOI
|
11 |
K. Sham et al., "I/O Staggering for Low-Power Jitter Reduction," 2008 38th EMC, Amsterdam, pp.1226-1229. 2008. DOI: 10.1109/EUMC.2008.4751682
DOI
|