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http://dx.doi.org/10.7471/ikeee.2019.23.2.461

Design of LUT-Based Decimation Filter for Continuous-Time PWM ADC  

Shim, Jae Hoon (School of Electronics Engineering, Kyungpook National University)
Publication Information
Journal of IKEEE / v.23, no.2, 2019 , pp. 461-468 More about this Journal
Abstract
A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.
Keywords
PWM; Continuous-time Loop Filter; Decimation; LUT; Mutli-rate Singal Processing;
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