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http://dx.doi.org/10.7471/ikeee.2019.23.2.454

Linearization Method Using Variable Capacitance in Inter-Stage Matching Networks for CMOS Power Amplifier  

Yoon, Jaehyuk (Agency for Defense Eevelopment)
Park, Changkun (School of Electronic Engineering, Soongsil University)
Publication Information
Journal of IKEEE / v.23, no.2, 2019 , pp. 454-460 More about this Journal
Abstract
In this paper, a watt-level 2.4-GHz RFCMOS linear power amplifier (PA) with pre-distortion method using variable capacitance with respect to input power is demonstrated. The proposed structure is composed of a power detector and a MOS capacitor to improve the linearity of the PA. The pre-distortion based linearizer is embedded in the two-stage PA to compensate for the gain compression in the amplifier stages, it also improves the output P1dB by approximately 1 dB. The simulation results demonstrate a 1-dB gain compression power of 30.81 dBm at 2.4-GHz, and PAE is 29.24 % at the output P1dB point.
Keywords
AM distortion; linearity; power amplifier; power detector; pre-distortion; virtual ground;
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