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http://dx.doi.org/10.7471/ikeee.2019.23.1.35

A 10-bit 20-MS/s Asynchronous SAR ADC using Self-calibrating CDAC  

Youn, Eun-ji (Department of Electronics Engineering, Kumoh National Institute of Technology)
Jang, Young-Chan (Department of Electronics Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.23, no.1, 2019 , pp. 35-43 More about this Journal
Abstract
A capacitor self-calibration is proposed to improve the linearity of the capacitor digital-to-analog converter (CDAC) for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with 10-bit resolution. The proposed capacitor self-calibration is performed so that the value of each capacitor of the upper 5 bits of the 10-bit CDAC is equal to the sum of the values of the lower capacitors. According to the behavioral simulation results, the proposed capacitor self-calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity (INL) from -0.810/+0.194 LSBs and -0.832/+0.832 LSBs to -0.235/+0.178 LSBs and -0.227/+0.227 LSBs, respectively, when the maximum capacitor mismatch of the CDAC is 4%. The proposed 10-bit 20-MS/s asynchronous SAR ADC is implemented using a 110-nm CMOS process with supply of 1.2 V. The area and power consumption of the proposed asynchronous SAR ADC are $0.205mm^2$ and 1.25 mW, respectively. The proposed asynchronous SAR ADC with the capacitor calibration has a effective number of bits (ENOBs) of 9.194 bits at a sampling rate of 20 MS/s about a $2.4-V_{PP}$ differential analog input with a frequency of 96.13 kHz.
Keywords
Asynchronous SAR ADC; Capacitor DAC; Capacitor self-calibration;
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