Browse > Article
http://dx.doi.org/10.7471/ikeee.2018.22.4.896

HDL Codes Generator for Cyclic Redundancy Check Codes  

Kim, Hyeon-kyu (Dept. of Electronics Engineering, Chungnam National University)
Yoo, Ho-young (Dept. of Electronics Engineering, Chungnam National University)
Publication Information
Journal of IKEEE / v.22, no.4, 2018 , pp. 896-900 More about this Journal
Abstract
Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.
Keywords
Parallel Processing; CRC Codes; VLSI DSP; Error Detection Code; EDA;
Citations & Related Records
연도 인용수 순위
  • Reference
1 C. Cheng and K. K. Parhi, "High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.53, no.10, pp.1017-1021, 2006. DOI:10.1109/TCSII.2006.882213   DOI
2 M. Ayinala and K. K. Parhi, "High-Speed Parallel Architectures for Linear Feedback Shift Registers," IEEE Transactions on Signal Processing, vol.59, no.9, pp.4459-4469, 2011. DOI:10.1109/TSP.2011.2159495   DOI
3 W. W. Peterson and D. T. Brown, "Cyclic Codes for Error Detection," Proceedings of the IRE, vol.49, 228-235, 1961. DOI:10.1109/JRPROC.1961.287814   DOI
4 G. Campobello et al. "Parallel CRC realization," IEEE Trans. on Computers vol.52, 1312-1319, 2003. DOI:10.1109/TC.2003.1234528   DOI
5 J. Jung et al, "Efficient Parallel Architecture for Linear Feedback Shift Regsiters," IEEE Trans. on Circuits and Sys. II - Express Brief, vol.62, no.11, 2015. DOI:10.1109/TCSII.2015.2456294   DOI
6 G. Albertango and R. Sisto, "Parallel CRC Generation," IEEE Micro, vol.10, no.5, 1990. DOI:10.1109/40.60527   DOI
7 E. Stavinov, "A Parallel CRC Generation Method," Circuits Celler Magzines for Computers, 2010.
8 C. Condo, M. Martina, G. Piccinini and G. Masera, "Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced," IEEE Signal Processing Letters, vol.21, no.11, pp.1380-1384, 2014. DOI:10.1109/LSP.2014.2334393   DOI
9 T. B. Pei, C. Zukowski, "High-speed parallel CRC circuits in VLSI," IEEE Trans. on Communications, vol.40, 653-657, 1992. DOI:10.1109/26.141415   DOI
10 M. Walma, "Pipelined Cyclic Redundancy Check (CRC) Calculation," 2007 16th International Conference on Computer Communications and Networks, pp. 365-370, 2007. DOI:10.1109/ICCCN.2007.4317846   DOI