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http://dx.doi.org/10.7471/ikeee.2018.22.4.886

An Optimized Hardware Implementation of SHA-3 Hash Functions  

Kim, Dong-Seong (School of Electronic Engineering, Kumoh National Institute of Technology)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.22, no.4, 2018 , pp. 886-895 More about this Journal
Abstract
This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.
Keywords
Secure Hash Algorithm-3; SHA-3; Hash function; KECCAK; Integrity; Digital Signature;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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