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http://dx.doi.org/10.7471/ikeee.2018.22.4.1158

A Fast-Locking All-Digital Frequency Multiplier  

Lee, Chang-Jun (Dept. of Electronic & Electrical Engineering, Hongik University)
Kim, Jong-Sun (Dept. of Electronic & Electrical Engineering, Hongik University)
Publication Information
Journal of IKEEE / v.22, no.4, 2018 , pp. 1158-1162 More about this Journal
Abstract
A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.
Keywords
Multiplying delay-locked loop; MDLL; Frequency Multiplier; Digital MDLL; Harmonic Lock;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 Ramin Farjad-Rad, William Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, M.-J. Edward Lee, "A low-power multiplying DLL for low jitter multigigahertz clock generation in highly integrated digital chips," IEEE J. Solid-State Circuits, vol.37, pp.1804-1812, 2002. DOI:10.1109/JSSC.2002.804340   DOI
2 R. Farjad-Rad, A. Nguyen, J. M. Tran, J. Poulton, W. Dally, J. Edmondson, R. Senthinathan, R. Rathi, M. Lee, and N. Hiok-Tiaq, "A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os," IEEE J. Solid-State Circuits, vol.39, pp.1553-1561, 2004.   DOI
3 S. Han, and Jongsun Kim, "Programmable fractional-ratio frequency multiplying clock generator," IET Electronics Letters, Vol.50, no.3, pp.163-165, 2014. DOI:10.1049/el.2013.2857   DOI
4 Jongsun Kim, "A fast-locking all-digital multiplying DLL for fractional-ratio dynamic frequency scaling," IEEE Transactions on Circuits and Systems II (TCAS-II), Vol.65, No.3, pp.276-280, 2018. DOI:10.1109/TCSII.2017.2688369   DOI
5 Jongsun Kim, et al, "An ahti-harmonic MDLL for phase aligned on-chip clock multiplication," IEICE Electronics Express, Vol.15, No.5, pp.1-11, 2018. DOI:10.1587/elex.15.20180042   DOI
6 S. Tam. S. Rusu, U. N. Desai, R. Kim, J. Zhang, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor," IEEE J. Solid-State Circuits, Vol.35, pp.1545-1552, 2000. DOI:10.1109/ISSCC.2000.839738   DOI
7 B. Kim, et al., "PLL/DLL system noise analysis for low jitter clock synthesizer design," in Proc. Int. Symp. Circuits and Systems, 1994. DOI:10.1109/ISCAS.1994.409189   DOI
8 G. Park, H. Kim, and Jongsun Kim, "A reset-free anti-harmonic programmable MDLL-based frequency multiplier," J. Semiconductor Technology and Science, Vol.13, no.5, pp.459-464, 2013. DOI:10.5573/JSTS.2013.13.5.459   DOI