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http://dx.doi.org/10.7471/ikeee.2018.22.2.233

A Cryptographic Processor Supporting ARIA/AES-based GCM Authenticated Encryption  

Sung, Byung-Yoon (School of Electronic Engineering, Kumoh National Institute of Technology)
Kim, Ki-Bbeum (Pixelplus Incorporated)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.22, no.2, 2018 , pp. 233-241 More about this Journal
Abstract
This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.
Keywords
Block cipher; authenticated encryption; AES; ARIA; GCM; GHASH;
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Times Cited By KSCI : 1  (Citation Analysis)
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