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http://dx.doi.org/10.7471/ikeee.2018.22.1.38

An Integrated Cryptographic Processor Supporting ARIA/AES Block Ciphers and Whirlpool Hash Function  

Kim, Ki-Bbeum (Pixelplus Inc.)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of IKEEE / v.22, no.1, 2018 , pp. 38-45 More about this Journal
Abstract
An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.
Keywords
ARIA; AES; Whirlpool; block cipher; hash function; cryptographic processor;
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Times Cited By KSCI : 1  (Citation Analysis)
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